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september 2008 rev 3 1/100 1 stm8af61xx, stm8ah61xx stm8af51xx, stm8ah51xx automotive 8-bit mcu, with up to 128 kbytes flash, eeprom, 10-bit adc, timers, lin, can, usart, spi, i 2 c, 3 v to 5.5 v features core max f cpu : 24 mhz advanced stm8a core with harvard architecture and 3-stage pipeline average 1.6 cycles/instruc tion resulting in 10 mips at 16 mhz f cpu for industry standard benchmark memories program memory: 48 to 128 kbytes flash; data retention 20 years at 55 c after 1 kcycle data memory: 1.5 to 2 kbytes true data eeprom; endurance 300 kcycles ram: 3 to 6 kbytes clock management low power crystal resonator oscillator with external clock input internal, user-trimmable 16 mhz rc and low power 128 khz rc oscillators clock security system with clock monitor reset and supply management multiple low power mode s (wait, slow, auto wake-up, halt) with user definable clock gating low consumption power-on and power-down reset interrupt management nested interrupt contro ller with 32 interrupt vectors up to 37 external interrupts on 5 vectors timers up to 2 auto-reload 16-bit pwm timers with up to 3 capcom channels each (ic, oc or pwm) multipurpose timer: 16-bit, 4 capcom channels, 3 complementary outputs, dead-time insertion and flexible synchronization 8-bit ar system timer with 8-bit prescaler auto wake-up timer two watchdog timers: window and standard communication interfaces high speed 1 mbit/s acti ve can 2.0b interface usart with clock output for synchronous operation - lin master mode linuart lin 2.1 comp liant, master/slave modes with automatic resynchronization spi interface up to 10 mbit/s or f cpu /2 i 2 c interface up to 400 kbit/s analog to digital converter (adc) 10-bit, 3 lsb adc with up to 16 multiplexed channels i/os up to 70 user pins including 10 high sink i/os highly robust i/o design, immune against current injection table 1. device summary (1) 1. this datasheet applies to product versions with and without data eeprom. the order code identifier is ?f? or ?h? respectively, only one of which appears in an order code. part numbers: stm8af61xx/stm8ah61xx stm8af/h61aa, stm8af/h 619a, stm8af/h61a9, stm8af/h6199, stm8af/h6189, stm8af/h6179, stm8af/h6169, stm8af/h 61a8, stm8af/h6198, stm8af/h6188, stm8af/h6178, stm8af/h6186, stm8af/h6176 part numbers: stm8af51xx/stm8ah51xx (can) stm8af/h51aa, stm8af/h 519a, stm8af/h51a9, stm8af/h5199, stm8af/h5189, stm8af/h5179, stm8af/h5169, stm8af/h 51a8, stm8af/h5198, stm8af/h5188, stm8af/h5178 lqfp80 14x14 lqfp48 7x7 lqfp32 7x7 lqfp64 10x10 www.st.com
contents stm8af61xx, stm8af51xx 2/100 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 product line-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 central processing unit stm8a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1.1 architecture and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1.2 addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1.3 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2 single wire interface module (swim) and debug module . . . . . . . . . . . . 13 5.2.1 swim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2.2 debug module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.3 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.4 non-volatile memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.4.1 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.4.2 write protection (wp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.4.3 read-out protection (rop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.4.4 speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.5 low-power operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.6 clock and clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.6.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.6.2 internal 16 mhz rc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.6.3 internal 128 khz rc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.6.4 internal high-speed crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.6.5 external clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.6.6 clock security system (css) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.7 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.7.1 watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.7.2 auto wake-up counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.7.3 multipurpose and pwm timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
stm8af61xx, stm8af51xx contents 3/100 5.7.4 timer 4: system timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.8 adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.9 communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.9.1 usart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.9.2 linuart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.9.3 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.9.4 i 2 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.9.5 can . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.10 input/output specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6 pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.1 package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.2.1 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8 interrupt table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9 register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10 option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 11.3.1 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 11.3.2 external clock sources and timing characteristics . . . . . . . . . . . . . . . . . 67 11.3.3 internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 69 11.3.4 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11.3.5 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
contents stm8af61xx, stm8af51xx 4/100 11.3.6 reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 11.3.7 tim 1, 2, 3, and 4 timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 78 11.3.8 spi serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 11.3.9 i 2 c interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 11.3.10 10-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 11.3.11 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 11.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 11.4.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 11.4.2 selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 89 12 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 12.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 13 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 14 stm8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 14.1 emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . 96 14.2 software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 14.2.1 stm8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 14.2.2 c and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 14.3 programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 15 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
stm8af61xx, stm8af51xx list of tables 5/100 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm8af/h51xx product line-up with can . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. stm8af/h61xx product line-up without can. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4. stm8a timer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 5. legend/abbreviation for table 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 6. stm8a microcontroller family pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 7. stack and ram partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 8. stm8a interrupt table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 9. stm8a i/o port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 10. stm8a general hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 11. cpu/swim/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 12. option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 13. option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 14. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 15. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 16. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 17. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 18. operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 19. total current consumption in run, wait and slow mode at v dd = 5.0 v. . . . . . . . . . . . . . . . 59 table 20. total current consumption and ti ming in halt, fast active halt and slow active halt modes at v dd = 5.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 21. total current consumption in run, wait and slow mode at v dd = 3.3 v. . . . . . . . . . . . . . . . 61 table 22. total current consumption and ti ming in halt, fast active halt and slow active halt modes at v dd = 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 23. typical peripheral current consumption v dd = 5.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 24. hse user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 table 25. hse oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 26. hsi oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 27. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 28. ram and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 29. flash program memory/data eeprom memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 30. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 31. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 32. tim 1, 2, 3 characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 33. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 34. i 2 c characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 35. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 36. adc accuracy with r ain < 10 k ? r ain , v dda = 3.3 v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 37. adc accuracy with r ain < 10 k ? , v dda = 5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 38. ems data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 39. emi data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 40. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 41. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 42. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 43. 80-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 44. 64-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 45. 48-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 46. 32-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
list of tables stm8af61xx, stm8af51xx 6/100 table 47. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
stm8af61xx, stm8af51xx list of figures 7/100 list of figures figure 1. stm8a block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 2. flash memory organization of stm8a products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 3. lqfp 80-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 4. lqfp 64-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 5. lqfp 48-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 6. lqfp 32-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 7. register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 8. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 9. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 10. f cpumax versus v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 11. typ. i dd(run)hse vs. v dd @f cpu = 16 mhz, periph = on . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 12. typ. i dd(run)hse vs. f cpu @v dd = 5.0 v, periph = on . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 13. typ. i dd(run)hsi vs. v dd @f cpu = 16 mhz, periph = off . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 14. typ. i dd(wfi)hse vs. v dd @f cpu = 16 mhz, periph = on . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 15. typ. i dd(wfi)hse vs. f cpu @v dd = 5.0 v, periph = on . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 16. typ. i dd(wfi)hsi vs. v dd @f cpu = 16 mhz, periph = off . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 17. hse external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 18. hse oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 19. typical hsi frequency vs v dd @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 20. typical lsi frequency vs v dd @ room temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 21. typical v il and v ih vs v dd @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 22. typical pull-up resistance r pu vs v dd @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . 73 figure 23. typical pull-up current i pu vs v dd @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 24. typ. v ol @ v dd = 3.3 v (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 25. typ. v ol @ v dd = 5.0 v (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 26. typ. v ol @ v dd = 3.3 v (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 27. typ. v ol @ v dd = 5.0 v (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 28. typ. v ol @ v dd = 3.3 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 29. typ. v ol @ v dd = 5.0 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 30. typ. v dd - v oh @ v dd = 3.3 v (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 31. typ. v dd - v oh @ v dd = 5.0 v (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 32. typ. v dd - v oh @ v dd = 3.3 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 33. typ. v dd - v oh @ v dd = 5.0 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 34. typical nrst v il and v ih vs v dd @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 35. typical nrst pull-up resistance r pu vs v dd @ four temperatures. . . . . . . . . . . . . . . . . . 77 figure 36. typical nrst pull-up current i pu vs v dd @ four temperatures . . . . . . . . . . . . . . . . . . . . . 77 figure 37. recommended reset pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 38. spi timing diagram where slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 39. spi timing diagram where slave mode and cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 40. spi timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 41. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 42. typical application with adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 43. 80-pin low profile quad flat package (14 x 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 44. 64-pin low profile quad flat package (10 x 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 45. 48-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 46. 32-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 47. stm8a order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
introduction stm8af61xx, stm8af51xx 8/100 1 introduction this datasheet refers to the stm8af61xx, stm8ah61xx, stm8af51xx, stm8ah51xx products with 48 to 128 kbytes of program memory. the stm8af51xx and stm8ah51xx are hereafter referred to as the stm8af/h51xx and the stm8af61xx and stm8ah61xx are hereafter referred to as the stm8af/h61xx. ?f? refers to product versions with data eeprom and ?h? refers to produc t versions without eeprom. th e identifiers ?f? and ?h? do not both appear in an order code. the datasheet contains the description of family features, pinout, electrical characteristics, mechanical data and ordering information. for complete information on the stm8a microcontroller memory, registers and peripherals, please refer to stm8a microcontroller family reference manual (rm0009). for information on programming, erasing and protection of the internal flash memory please refer to the stm8 flash programming manual (pm0047). for information on the debug and swim (single wire interface module) refer to the stm8 swim communication protocol and debug module user manual (um0470). for information on the stm8 core, please refer to the stm8 cpu programming manual (pm0044).
stm8af61xx, stm8af 51xx description 9/100 2 description the stm8a automotive 8-bit microcontrollers offer from 48 to 128 kbytes of program memory and integrat ed true data eeprom. the stm8af/h51xx series feature a can interface. all devices of the stm8a product line provide the following benefits: reduced system cost ? integrated true data eeprom for up to 300 k write/erase cycles ? high system integration level with intern al clock oscillators, watchdog and brown- out reset performance and robustness ? peak performance 20 mips at 24 mhz and average performance 10 mips at 16 mhz cpu clock frequency ? robust i/o, independent watchdogs with separate clock source ? clock security system short development cycles ? applications scalability across a common family product architecture with compatible pinout, memory map and and modular peripherals. ? full documentation and a wide choice of development tools product longevity ? advanced core and peripherals made in a state-of-the art technology ? native automotive product family operating both at 3.3 v and 5 v supply all stm8a and st7 microcontrollers are supported by the same tools including stvd/stvp development environment, the stice emulator and a low-cost, third party in- circuit debugging tool (for more details, see section 14: stm8 development tools on page 96 ).
product line-up stm8af61xx, stm8af51xx 10/100 3 product line-up . 2 table 2. stm8af/h51xx product line-up with can order code package prog. (bytes) ram (bytes) data ee (bytes) 10-bit a/d ch. timers (ic/oc/pwm) serial interfaces i/0 wakeup pins stm8af/h51aat lqfp80 (14x14) 128 k 6 k 2 k 16 1x8-bit: tim4 3x16-bit: tim1, tim2, tim3 (9/9/9) can, lin(uart), spi, usart, i2c 72/37 stm8af/h519at 96 k stm8af/h51a9t lqfp64 (10x10) 128 k 56/36 stm8af/h5199t 96 k stm8af/h5189t 64 k 4 k 1.5 k stm8af/h5179t 48 k 3 k stm8af/h5169t 32 k 2 k 1 k stm8af/h51a8t lqfp48 (7x7) (1) 1. qfn package planned 128 k 6 k 2 k 10 40/35 stm8af/h5198t 96 k stm8af/h5188t 64 k 4 k 1.5 k stm8af/h5178t 48 k 3 k table 3. stm8af/h61xx product line-up without can order code package prog. (bytes) ram (bytes) data ee (bytes) 10-bit a/d ch. timers (ic/oc/pwm) serial interfaces i/0 wakeup pins stm8af/h61aat lqfp80 (14x14) 128 k 6 k 2 k 16 1x8-bit: tim4 3x16-bit: tim1, tim2, tim3 (9/9/9) lin(uart), spi, usart, i2c 72/37 stm8af/h619at 96 k stm8af/h61a9t lqfp64 (10x10) 128 k 56/36 stm8af/h6199t 96 k stm8af/h6189t 64 k 4 k 1.5 k stm8af/h6179t 48 k 3 k stm8af/h6169t 32 k 2 k 1 k stm8af/h61a8t lqfp48 (7x7) (1) 1. qfn package planned 128 k 6 k 2 k 10 40/35 stm8af/h6198t 96 k stm8af/h6188t 64 k 4 k 1.5 k stm8af/h6178t 48 k 3 k stm8af/h6186t lqfp32 (7x7) (1) 64 k 4 k 7 1x8-bit: tim4 3x16-bit: tim1, tim2, tim3 (8/8/8) lin(uart), spi, i2c 25/23 stm8af/h6176t 48 k 3 k
stm8af61xx, stm8af51xx block diagram 11/100 4 block diagram figure 1. stm8a block diagram xtal 1-24 mhz rc int. 16 mhz rc int. 128 khz stm8a core debug/swim i 2 c spi usart linuart 16-bit pwm timers awu timer reset block reset por pdr clock controller detector clock to peripherals and core 10 mbit/s lin master 16 channels window wdg wdg up to 128 kbyte up to 2 kbytes up to 6 kbytes boot rom 10-bit adc becan 9 capcom reset 400 kbit/s 1 mbit/s master/slave single wire autosynchro debug interf. spi emul. channels program flash 16-bit multi-purpose timer (tim1) (tim2, tim3) 8-bit ar timer (tim4) data eeprom ram up to address and data bus
product overview stm8af61xx, stm8af51xx 12/100 5 product overview the following section intends to give an overview of the basic features of the stm8a functional modules and peripherals. for more detailed information please refer to the stm8a microcontroller family reference manual (rm0009). 5.1 central processing unit stm8a the 8-bit stm8a core is designed for code efficiency and performance. it contains 21 internal registers (six directly addressable in each execution context), 20 addressing modes including indexed indirect and relative addressing and 80 instructions. 5.1.1 architecture and registers harvard architecture 3-stage pipeline 32-bit wide program memory bus with single cycle fetching for most instructions x and y 16-bit index registers, enabling indexed addressing modes with or without offset and read-modify-write type data manipulations 8-bit accumulator 24-bit program counter with 16-mbyte linear memory space 16-bit stack pointer with access to a 64 kbyte stack 8-bit condition code register with seven condition flags for the result of the last instruction 5.1.2 addressing 20 addressing modes indexed indirect addressing mode for look-up tables located anywhere in the address space stack pointer relative addressing mode for local variables and parameter passing 5.1.3 instruction set 80 instructions with 2-byte average instruction size standard data movement and logic/arithmetic functions 8-bit by 8-bit multiplication 16-bit by 8-bit and 16-bit by 16-bit division bit manipulation data transfer between stack and accumulator (push/pop) with direct stack access data transfer using the x and y registers or direct memory-to-memory transfers
stm8af61xx, stm8af51xx product overview 13/100 5.2 single wire interface mo dule (swim) and debug module the single wire interface module, swim, together with an integrated debug module, permits non-intrusive, real-time in-circuit debugging and fast memory programming. 5.2.1 swim single wire interface for direct access to the debugging module and memory programming. the interface can be activated in all device operation modes and supports hot-plugging. the maximum data transmission speed is 145 bytes/ms. 5.2.2 debug module the non-intrusive debugging module features a performance close to a full-featured emulator. besides memory and peripheral operation, cpu operation can also be monitored in real-time by means of shadow registers. r/w of ram and peripheral registers in real-time r/w for all resources when th e application is stopped breakpoints on all program-memory instructions (software breakpoints) except the vector table two advanced breakpoints and 23 predefined configurations 5.3 interrupt controller nested interrupts with three software priority levels 32 interrupt vectors with hardware priority up to 37 external interrupts on five vectors trap and reset interrupts 5.4 non-volatile memory up to 128 kbytes of program single voltage flash memory up to 2 kbytes true (n ot emulated) data eeprom read while write: writing in the data memory is possible while executing code in the program memory 128 user option bytes permit permanent device set up 5.4.1 architecture array: up to 128 kbytes of flash program memory organized in blocks of 128 bytes each read granularity: 1 word = 4 bytes write/erase granularity: 1 word (4 bytes) or 1 block (128 bytes) in parallel writing, erasing, word and block register management is handled automatically by the memory interface.
product overview stm8af61xx, stm8af51xx 14/100 5.4.2 write protection (wp) write protection in application mode is intended to avoid unintentional overwriting of the memory in case of user software malfunctio n. code update in user mode is still possible after execution of a specific mass key sequence. the program memory is divided into two areas: main program memory: up to 128 kbytes minus user-specific boot code (ubc) ubc: configurable up to 128 kbytes the ubc area also remains write-protected during in-application programming. it permits storage of the boot program or specific code libraries. the boot area is a part of the program memory that contains the reset and interrupt vectors, the reset routine and usually the iap and communication routines. the ubc area has a second level of protection to prevent unintentional erasing or modification during iap programming. this means that the mass keys do not unlock the ubc area. the size of the ubc is programmable through the ubc option byte, in increments of 512 bytes, by programming the ubc option byte in icp mode. figure 2. flash memory organization of stm8a products programmable area from 1 kbyte data ubc area program memory area data memory area (2 kbytes) (first two pages) up to program memory eeprom remains write protected during iap memory write access possible for iap option bytes end - maximum 128 kbytes flash program memory
stm8af61xx, stm8af51xx product overview 15/100 5.4.3 read-out protection (rop) stm8a devices provide a read-out protection of the code and data memory by programming the lock byte at address 4800h with the value aah. read-out protection prevents reading and writing the program and data memory via the debug module and swim interface. this protection is active in all device operation modes. any attempt to remove the protection by overwriting the lock byte triggers a global erase of the program and data memory. the rop circuit may provide a temporary access for debugging or failure analysis. this is a specific product option and must be specified while ordering stm8a products. temporary read access is protected by a user defined, 8-byte keyword that is different from 00h or ffh. the keys are stored in the option byte area. temporary read-out can be permanently disabled by means of the option byte tmu_dis. for enabling temporary read access the eight access keys have to be written in the tmu registers. a wrong code does not change the protection status. more than eight unsuccessful access trials trigger an erase of the program and data memory. entering the right key sequence enables a temporary read access to the code and data memory after a delay of several milliseconds. the procedure for temporary read access is as follows: activate swim mode under device reset - the cpu is stalled, code and data memory are not visible by the debug module. enable the internal 128 khz lsi oscillator write the 8eight key bytes into the tmu registers set the bit(0) of the tmu status register to 1. a dedicated state machine on an isolated bus, compares the tmu register content with the key stored in the tmu option bytes. during this periode read and write operations have no effect. a reset re-activates the initial protection status. the comparison can be monitored by means of the tu_ctl_st register. in case of a successful key comparison, the swim interface enables read access to the code and data memory and program execution. a comparison error does not change the protection status but increments the counter maxatt. if the counter content exceedes eight unsuccessful trials, a glo bal erase of the data and code memory is triggered. the read access is temporary. a device reset restores the initial protection. 5.4.4 speed operation at up to 16 mhz cpu clock frequency without wait states. at a higher clock frequency, a single wait state has to be inserted. programming time modes (same for word or block) ? fast programming: without erase ? standard programming: erase and program
product overview stm8af61xx, stm8af51xx 16/100 5.5 low-power operating modes the product features various low-power modes: slow mode: prescaled cpu clock, selected peripherals at full clock speed active halt mode: cpu and peripheral clocks are stopped halt mode: cpu and peripheral clocks are stopped, the device remains powered on. wake-up is triggered by an external interrupt. in all modes the cpu and peripherals remain permanently powered on, the system clock is applied only to selected modules. the ram content is preserved and the brown-out reset circuit remains activated. 5.6 clock and clock controller the clock controller distributes the system clock coming from different o scillators to the core and the peripherals. it also manages clock gating for low power modes and ensures clock robustness. 5.6.1 features clock sources: ? internal 16 mhz and 128 khz rc oscillators ? crystal oscillator ? external clock input reset: after reset the microcontroller restarts by default with an internal 2-mhz clock (16 mhz/8). the prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register. the clock signal is not switched until the new clock source is ready. the design guarantees glitch-free switching. clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. wake-up: recovery from halt and awu (auto wake-up) low power modes uses the internal rc oscillator (16 mhz/8) for quick start-up and then switches to the last selected clock source before halt mode is entered. clock security system (css): the css permits monitoring of external clock sources and automatic switching to the internal rc (16 mhz/8) in case of a clock failure. configurable main clock output (cco): this outputs an external clock for use by the application.
stm8af61xx, stm8af51xx product overview 17/100 5.6.2 internal 16 mhz rc oscillator default clock after reset 2 mhz (16 mhz/8) wake-up time: < 2 s user trimming the register clk_hsitrimr with two trimming bits plus one additional bit for the sign permits frequency tuning to a precision of 1% by the application program. the trimming step granularity is 1.5 %. the adjustment range covers all possible frequency variations versus supply voltage and temperature. this trimming does not change the initial production setting. 5.6.3 internal 128 khz rc oscillator the frequency of this clock is 128 khz and it is independent from the main clock. it drives the watchdog or the awu wake-up timer. in systems which do not need independent clock sources for the watchdog counters, the 128 khz signal can be used as the system clock. this configuration has to be enabled by setting an option byte (opt3, lsi_en). 5.6.4 internal high-speed crystal oscillator the internal high-speed crysta l oscillator delivers the main clock in normal run mode. it operates with quartz crystals and ceramic resonators. frequency range: 1 to 24 mhz crystal oscillation mode: preferred fundamental i/os: standard i/o pins mu ltiplexed with oscin, oscout optionally, an external clock signal can be injected into the oscin input pin. 5.6.5 external clock input the external clock signal is applied to the oscin input pin of the crystal oscillator. the frequency range is 0 to 24 mhz. 5.6.6 clock securit y system (css) the clock security system protects against a syste m stall in case of an external crystal clock failure. in case of a clock failure an interrupt is generated and the high speed internal clock (hsi) is automatically selected with a frequency of 2 mhz (16 mhz/8). this function can be enabled using the css register (clk_cssr). the css operates by detecting when the external clock signal (crystal or external clock) falls below 500 khz. with active css th is is the minimum operating frequency.
product overview stm8af61xx, stm8af51xx 18/100 5.7 timers 5.7.1 watchdog timers the watchdog system is based on two independent timers providing maximum security to the applications. the wdg timer activity is controlled by the application program or option bytes. once the watchdog is activated, it cannot be disabled by the user program without a reset. window watchdog timer the window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence. the window function can be used to trim the watchdog behavior to match the application perfectly. the application software must refresh the counter before time-out and during a limited time window. a reset is generated in two situations: 1. timeout 2. refresh out of window: the downcounter is refreshed before its value is lower then the one stored in the window register. independent watchdog timer the independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures. it is clocked by the 128 khz lsi internal rc clock source, and thus stays active even in case of a cpu clock failure. if the hardware watchdog feature is enabled through the device option bits, the watchdog is automatically enabled at power-on, and generates a reset unless the key register is written by software before the counter reaches the end of count. the iwdg time base spans from 60 s to 1 s. it can be adjusted by setting the registers of the 7-bit prescaler and 8-bit down-counter. 5.7.2 auto wake-up counter used for auto wake-up from active halt mode. clock source: internal 128 khz internal lo w frequency rc oscillator or external clock.
stm8af61xx, stm8af51xx product overview 19/100 5.7.3 multipurpose and pwm timers stm8a devices described in this datasheet, contain up to three 16-bit multipurpose and pwm timers providing nine capcom channels in total. timer 1: multipurpose pwm timer this is a high-end timer designed for a wide range of control applications. with its complementary outputs, dead-ti me control and center-aligned pwm capability, the field of applications is extended to motor control, lighting and half-bridge driver. 16-bit up, down and up/down ar (auto-reload) counter with 16-bit prescaler four independent capcom channels configurable as input capture, output compare, pwm generation (edge and center aligned mode) and single pulse mode output trigger module which allows th e interaction of timer 1 with other timers or the adc to be controlled break input to force the timer outputs into a defined state three complementary outputs with adjustable dead time interrupt sources: 4 x input capture/output compare, 1 x overflow/update, 1 x break timer 2 and 3: 16-bit pwm timers 16-bit auto-reload up-counter 15-bit prescaler adjustable to fixed power of two ratios 1?32768 timers with three or two individually configurable capcom channels interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update 5.7.4 timer 4: system timer 8-bit auto-reload, adjustable prescaler ratio to any power of two from 1 to 128 clock source: master clock interrupt source: 1 x overflow/update table 4. stm8a timer configuration timer counter prescaler type capcom complementary outputs synchronization module timer1 16 16 up/down 4 3 yes timer2 15-bit fixed power of 2 ratios up 3 0no timer3 2 timer4 8 7-bit fixed power of 2 ratios 0
product overview stm8af61xx, stm8af51xx 20/100 5.8 adc the stm8a products described in this datasheet, contain a 10-bit successive approximation adc with 16 multiplexed input channels. general features: 10-bit adc with up to 16 channels input voltage range: 0 to v dda acqusition modes ? single conversion ? continous acquisition - up to 100 ksamples/s effective sampling rate ? trigger register and external trigger input interrupts ? end of conversion (eoc) - can be masked 5.9 communication interfaces the following communication interfaces are implemented on stm8a products: usart: full feature uart, spi em ulation, lin ma ster capability linuart: lin2.1 master/slave capability, full feature uart spi - full and half-duplex, 10 mbit/s i2c - up to 400 kbit/s can (rev. 2.0a,b) - 3 tx mailboxes - up to 1 mbit/s swim for debugging and device programming 5.9.1 usart main features 1 mbit/s full duplex sci lin master capable spi emulation 16-bit baud-rate prescaler
stm8af61xx, stm8af51xx product overview 21/100 full duplex, asynchronous communication nrz standard format (mark/space) high-precision baud rate generator system ? common programmable transmit and receive baud rates up to 2.5 m baud programmable data word length (8 or 9 bits) configurable stop bits providing support for 1 or 2 stop bits lin master mode ? lin break and delimiter generation ? lin break and delimiter detection with separate flag and interrupt source for read- back checking transmitter clock output for synchronous communication single wire half duplex communication separate enable bits for transmitter and receiver transfer detection flags ? receive buffer full ? transmit buffer empty ? end of transmission flags parity control: ? transmit parity bit ? check parity of received data byte four error detection flags ? overrun error ? noise error ?frame error ? parity error six interrupt sources with flags ? transmit data register empty ? transmission complete ? receive data register full ? idle line received ? parity error ? lin break and delimiter detection two interrupt vectors ? transmitter interrupt ? receiver interrupt reduced power consumption mode multi-processor communication, allowing entry into mute mode if address match does not occur wakeup from mute mode (by idle line detection or address mark detection) two receiver wakeup modes: ? address bit (msb) ? idle line
product overview stm8af61xx, stm8af51xx 22/100 5.9.2 linuart main features lin master/slave rev. 2.1 compliant auto-synchronization in lin slave mode 16-bit baud rate prescaler 1 mbit full duplex sci lin master autonomous header handling 13-bit lin synch break generation lin slave autonomous header handling - one single interrupt per valid message header automatic baud rate synchronization - maximum tolerated initial clock deviation 15 % synch delimiter checking 11-bit lin synch break detection - break detection always active parity check on the lin identifier field lin error management hot plugging support asynchronous communication (uart) full duplex, asynchronous communications - nrz standard format (mark/space) independently programmable transmit and receive baud rates up to 500 kbit/s programmable data word length (8 or 9 bits) low-power standby mode - two receiver wake-up modes: ? address bit (msb) ? idle line muting function for multiprocessor configurations overrun, noise and frame error detection six interrupt sources tx, rx parity control 5.9.3 spi maximum speed: 10 mbit/s or f cpu /2 both for master and slave full duplex synchronous transfers simplex synchronous transfers on two lines with a possible bidirectional data line master or slave operation - selectable by hardware or software crc calculation 1 byte tx and rx buffer slave/master selection input pin
stm8af61xx, stm8af51xx product overview 23/100 5.9.4 i 2 c i 2 c master features: ? clock generation ? start and stop generation i 2 c slave features: ? programmable i 2 c address detection ? stop bit detection generation and detection of 7-bit/10-bit addressing and general call supports different communication speeds: ? standard speed (up to 100 khz), ? fast speed (up to 400 khz) interrupt: ? successful address/data communication ? error condition ? wake-up from halt wake-up from halt on address detection in slave mode 5.9.5 can the becan3 controller (basic enhanced can), interfaces the can network and supports the can protocol version 2.0a and b. it has been designed to manage a high number of incoming messages efficiently with a minimum cpu load. for safety-critical applications, the can controller provides all hardware functions to support the can time triggered communication option (ttcan). the maximum transmission speed is 1 mbit. transmission three transmit mailboxes configurable transmit priority by identifier or order request time stamp on sof transmission reception 11- and 29-bit id 1 receive fifo (3 messages deep) software-efficient mailbox mapping at a unique address space fmi (filter match index) stored with message configurable fifo overrun time stamp on sof reception 6 filter banks, 2 x 32 bytes (scalable to 4 x 16-bit) each, enabling various masking configurations, such as 12 filters for 29-bit id or 48 filters for 11-bit id
product overview stm8af61xx, stm8af51xx 24/100 filtering modes: ? mask mode permitting id range filtering ? id list mode time triggered communication option ? disable automatic retransmission mode ? 16-bit free running timer ? configurable timer resolution ? time stamp sent in last two data bytes interrupt management maskable interrupt software-efficient mailbox mapping at a unique address space 5.10 input/output specifications the product features four different i/o types: standard i/o 2 mhz fast i/o 10 mhz high sink 8 ma, 2 mhz true open drain (i 2 c interface) to decrease emi (electromagnetic interference), high sink i/os have a limited maximum slew rate. the rise and fall times are similar to those of standard i/os. selected i/os include a low leakage analog switch. stm8a i/os are designed to withstand current injection. for a negative injection current of 4 ma, the resulting leakage current in the adjacent input does not exceed 1 a. external protection diodes are no longer required.
stm8af61xx, stm8af51xx pinouts and pin description 25/100 6 pinouts and pin description 6.1 package pinouts figure 3. lqfp 80-pin pinout 1. the can interface is only avail able on the stm8af/h51xx product line pd4 (hs)/tim2_cc1/beep 2 1 3 4 5 6 7 8 10 9 12 14 16 18 20 11 15 13 17 19 25 26 28 27 30 32 34 36 38 29 33 31 35 37 39 57 58 56 55 54 53 52 51 49 50 47 45 43 41 48 44 46 42 60 59 61 62 63 64 66 68 65 67 69 70 71 72 74 73 75 76 77 78 79 80 pi4 pi3 pi2 pi1 pc4 (hs)/tim1_cc4 pc3 (hs)/tim1_cc3 pc2 (hs)/tim1_cc2 pc1 (hs)/tim1_cc1 pg6 pg5 pi5 pi0 pg4 pg3 pg2 pc7/spi_miso v ssio_2 v ddio_1 tim2_cc3/pa3 usart_rx/pa4 usart_tx/pa5 ain12/pf4 v ssio_1 v ss vcap v dd usart_ck/pa6 (hs) ph0 ( hs) ph1 ph2 ph3 ain15/pf7 ain14/pf6 ain13/pf5 nrst oscin/pa1 oscout/pa2 ain5/pb5 ain4/pb4 ain1/pb1 ain0/pb0 ain8/pe7 v ref- ain10/pf0 ain7/pb7 ain6/pb6 tim1_etr/ph4 tim1_ncc3/ph5 tim1_ncc2/ph6 40 ain9/pe6 21 22 24 23 ain11/pf3 v ref+ v dda v ssa pd0 (hs)/tim3_cc2 pe2/i 2c_sda pe3/tim1_bkin pe4 pg7 pd7/tli pd6/linuart_rx pd5/linuart_tx pi7 pi6 pd2 (hs)/tim3_cc1 pd1 (hs)/swim pc5/spi_sck pc6/spi_mosi pg0/can_tx (1) pg1/can_rx (1) pe0/clk_cco pd3 (hs)/tim2_cc2 ain3/pb3 ain2/pb2 pc0/adc_etr pe5/spi_nss tim1_ncc1/ph7 v ddio_2 pe1/i2c_scl (hs) high sink capability
pinouts and pin description stm8af61xx, stm8af51xx 26/100 figure 4. lqfp 64-pin pinout 1. the can interface is only avail able on the stm8af/h51xx product line v ref- ain10/pf0 ain7/pb7 ain6/pb6 ain5/pb5 ain4/pb4 tim1_etr/ain3/pb3 tim1_ncc3/ain2/pb2 tim1_ncc2/ain1/pb1 tim1_ncc1/ain0/pb0 ain8/pe7 ain9/pe6 ain11/pf3 v ref+ v dda v ssa 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v ss vcap v dd v ddio_1 tim2_cc3/pa3 usart_rx/pa4 usart_tx/pa5 usart_ck/pa6 ain15/pf7 ain14/pf6 ain13/pf5 ain12/pf4 nrst oscin/pa1 oscout/pa2 v ssio_1 pg1/can_rx (1) pg0/can_tx (1) pc7/spi_miso pc6/spi_mosi v ddio_2 v ssio_2 pc5/spi_sck pc4 (hs)/tim1_cc4 pc3 (hs)/tim1_cc3 pc2 (hs)/tim1_cc2 pc1 (hs)/tim1_cc1 pe5/spi_nss pi0 pg4 pg3 pg2 pd3 (hs)/tim2_cc2/adc_etr pd2 (hs)/tim3_cc1 pd1 (hs)/swim pd0 (hs)/tim3_cc2 pe0/clk_cco pe1/i2c_scl pe2/i2c_sda pe3/tim1_bkin pe4 pg7 pg6 pg5 pd7/tli pd6/linuart_rx pd5/linuart_tx pd4 (hs)/tim2_cc1/ beep (hs) high sink capability
stm8af61xx, stm8af51xx pinouts and pin description 27/100 figure 5. lqfp 48-pin pinout 1. the can interface is only avail able on the stm8af/h51xx product line 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 48 47 46 45 pa6 ain8/pe7 pc1 (hs)/tim1_cc1 pe5/spi_nss pg1 ain9/pe6 pd3 (hs)/tim2_cc2/adc_etr pd2 (hs)/tim3_cc1 pe0/clk_cco pe1/i 2 c_scl pe2/i 2 c_sda pe3/tim1_bkin pd7/tli pd6/linuart_rx pd5/linuart_tx pd4 (hs)/tim2_cc1/beep pd1 (hs)/swim pd0 (hs)/tim3_cc2 v ssio_2 pc5/spi_sck pc4 (hs)/tim1_cc4 pc3 (hs)/tim1_cc3 p c2 (hs)/tim1_cc2 pg0 pc7/spi_miso pc6/spi_mosi v ddio_2 ain7/pb7 ain6/pb6 ain5/pb5 ain4/pb4 tim1_etr/ain3/pb3 tim1_ncc3/ain2/pb2 tim1_ncc2/ain1/pb1 tim1_ncc1/ain0/pb0 v dda v ssa v ss vcap v dd v ddio_1 tim2_cc3/pa3 pa4 pa5 nrst oscin/pa1 oscout/pa2 v ssio_1 (hs) high sink capability
pinouts and pin description stm8af61xx, stm8af51xx 28/100 figure 6. lqfp 32-pin pinout 6.2 pin description reset state is shown in bold . i2c_scl/ain4/pb4 tim1_etr/ain3/pb3 tim1_ncc3/ain2/pb2 tim1_ncc2/ain1/pb1 tim1_ncc1/ain0/pb0 v dda v ssa i2c_sda/ain5/pb5 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10111213141516 1 2 3 4 5 6 7 8 vcap v dd v ddio ain12/pf4 nrst oscin/pa1 oscout/pa2 v ss pc3 (hs)/tim1_cc3 pc2 (hs)/tim1_cc2 pc1 (hs)/tim1_cc1 pe5/spi_nss pc7/spi_miso pc6/spi_mosi pc5/spi_sck pc4 (hs)/tim1_cc4 pd3 (hs)/tim2_cc2/adc_etr pd2 (hs)/tim3_cc1/tim2_cc3 pd1 (hs)/swim pd0 (hs)/tim3_cc2/clk_cco/tim1_brk pd7/tli pd6/linuart_rx pd5/linuart_tx pd4 (hs)/tim2_cc1/beep (hs) high sink capability table 5. legend/abbreviation for table 6 type i= input, o = output, s = power supply level input cm = cmos (standard for all i/os) output hs = high sink (8 ma) output speed o1 = standard (up to 2 mhz) o2 = fast (up to 10 mhz) o3 = fast/slow programmability with slow as default state after reset o4 = fast/slow programmability with fast as default state after reset port and control configuration input float = floating, wpu = weak pull-up output t = true open drain, od = open drain, pp = push pull
stm8af61xx, stm8af51xx pinouts and pin description 29/100 table 6. stm8a microcontroller family pin description pin number pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] lqfp80 lqfp64 lqfp48 lqfp32 floating wpu ext. interrupt high sink speed od pp 1111nrst i/o x reset 2222pa1/oscin i/o x xo1xx port a1 resonator/crystal in 3333pa2/oscout i/o x xx o1xx port a2 resonator/crystal out 444 -v ssio_1 s i/o ground 5554v ss s digital ground 6665vcap s 1.8 v regulator capacitor 7776v dd s digital power supply 8887v ddio_1 s i/o power supply 9 9 9 - pa3/tim2_cc3 i/o x xx o1xx port a3 timer 2 - channel3 tim3_cc1 [afr1] 10 10 10 - pa4/usart_rx i/o x xx o3xx port a4 usart receive 11 11 11 - pa5/usart_tx i/o x xx o3xx port a5 usart transmit 12 12 12 - pa6/usart_ck i/o x xx o3xx port a6 usart synchronous clock 13---ph0 i/o x xhso3xx port h0 14---ph1 i/o x xhso3xx port h1 15---ph2 i/o x xo1xx port h2 16---ph3 i/o x xo1xx port h3 17 13 - - pf7/ain15 i/o x xo1xx port f7 analog input 15 18 14 - - pf6/ain14 i/o x xo1xx port f6 analog input 14 19 15 - - pf5/ain13 i/o x xo1xx port f5 analog input 13 20 16 - 8 pf4/ain12 i/o x xo1xx port f4 analog input 12 21 17 - - pf3/ain11 i/o x xo1xx port f3 analog input 11 22 18 - - v ref+ s adc positive reference voltage 23 19 13 9 v dda s analog power supply 24 20 14 10 v ssa s analog ground 25 21 - - v ref- s adc negative reference voltage 26 22 - - pf0/ain10 i/o x xo1xx port f0 analog input 10
pinouts and pin description stm8af61xx, stm8af51xx 30/100 27 23 15 - pb7/ain7 i/o x xx o1xx port b7 analog input 7 28 24 16 - pb6/ain6 i/o x xx o1xx port b6 analog input 6 29 25 17 11 pb5/ain5 i/o x xx o1xx port b5 analog input 5 i 2 c_sda [afr6] 30 26 18 12 pb4/ain4 i/o x xx o1xx port b4 analog input 4 i 2 c_scl [afr6] 31 27 19 13 pb3/ain3 i/o x xx o1xx port b3 analog input 3 tim1_etr [afr5] 32 28 20 14 pb2/ain2 i/o x xx o1xx port b2 analog input tim1_ ncc3 [afr5] 33 29 21 15 pb1/ain1 i/o x xx o1xx port b1 analog input 1 tim1_ ncc2 [afr5] 34 30 22 16 pb0/ain0 i/o x xx o1xx port b0 analog input 0 tim1_ ncc1 [afr5] 35 - - - ph4/tim1_etr i/o x xo1xx port h4 timer 1 - trigger input 36 - - - ph5/ tim1_ncc3 i/o x xo1xx port h5 timer 1 - inverted channel 3 37 - - - ph6/tim1_ncc2 i/o x xo1xx port h6 timer 1 - inverted channel 2 38 - - - ph7/tim1_ncc1 i/o x xo1xx port h7 timer 1 - inverted channel 2 39 31 23 - pe7/ain8 i/o x xo1xx port e7 analog input 8 40 32 24 pe6/ain9 i/o x xx o1xx port e7 analog input 9 41 33 25 17 pe5/spi_nss i/o x xx o1xx port e5 spi master/slave select 42 - - - pc0/adc_etr i/o x xx o1xx port c0 adc trigger input 43 34 26 18 pc1/tim1_cc1 i/o x xxhso3xx port c1 timer 1 - channel 1 44 35 27 19 pc2/tim1_cc2 i/o x xxhso3xx port c2 timer 1- channel 2 45 36 28 20 pc3/tim1_cc3 i/o x xxhso3xx port c3 timer 1 - channel 3 table 6. stm8a microcontroller family pin description (continued) pin number pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] lqfp80 lqfp64 lqfp48 lqfp32 floating wpu ext. interrupt high sink speed od pp
stm8af61xx, stm8af51xx pinouts and pin description 31/100 46 37 29 21 pc4/tim1_cc4 i/o x xxhso3xx port c4 timer 1 - channel 4 47 38 30 22 pc5/spi_sck i/o x xx o3xx port c5 spi clock 48 39 31 - v ssio_2 s i/o ground 49 40 32 - v ddio_2 s i/o power supply 50 41 33 23 pc6/spi_mosi i/o x xx o3xx port c6 spi master out/ slave in 51 42 34 24 pc7/spi_miso i/o x xx o3xx port c7 spi master in/ slave out 52 43 35 - pg0/can_tx i/o x xo1xx port g0 can transmit 53 44 36 - pg1/can_rx i/o x xo1xx port g1 can receive 54 45 - - pg2 i/o x xo1xx port g2 55 46 - - pg3 i/o x xo1xx port g3 56 47 - - pg4 i/o x xo1xx port g4 57 48 - - pi0 i/o x xo1xx port i0 58---pi1 i/o x xo1xx port i1 59---pi2 i/o x xo1xx port i2 60---pi3 i/o x xo1xx port i3 61---pi4 i/o x xo1xx port i4 62---pi5 i/o x xo1xx port i5 63 49 - - pg5 i/o x xo1xx port g5 64 50 - - pg6 i/o x xo1xx port g6 65 51 - - pg7 i/o x xo1xx port g7 66 52 - - pe4 i/o x xx o1xx port e4 67 53 37 - pe3/tim1_bkin i/o x xx o1xx port e3 timer 1 - break input 68 54 38 - pe2/i 2 c_sda i/o x xx o1t (1) x port e2 i 2 c data 69 55 39 - pe1/i 2 c_scl i/o x xx o1t (1) x port e1 i 2 c clock 70 56 40 - pe0/clk_cco i/o x xx o3xx port e0 configurable clock output 71---pi6 i/o x xo1xx port i6 72---pi7 i/o x xo1xx port i7 table 6. stm8a microcontroller family pin description (continued) pin number pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] lqfp80 lqfp64 lqfp48 lqfp32 floating wpu ext. interrupt high sink speed od pp
pinouts and pin description stm8af61xx, stm8af51xx 32/100 6.2.1 alternate function remapping as shown in the rightmost column of ta bl e 6 , some alternate functions can be remapped at different i/o ports by programming one of eight afr (alternate function remap) option bits. refer to section 10: option bytes on page 49 . when the remapping option is active, the default alternate function is no longer available. to use an alternate function, the corresponding peripheral must be enabled in the peripheral registers. alternate function remappi ng does not effect gpio capabilities of the i/o ports (see the gpio section of the stm8a microcontroller family reference manual, rm0009). 73 57 41 25 pd0/tim3_cc2 i/o x xxhso3xx port d0 timer 3 - channel 2 tim1_bkin [afr3]/ clk_cco [afr2] 74 58 42 26 pd1/swim i/o x x xhso4x x port d1 swim data interface 75 59 43 27 pd2/tim3_cc1 i/o x xxhso3xx port d2 timer 3 - channel 1 tim2_cc3 [afr1] 76 60 44 28 pd3/tim2_cc2 i/o x xxhso3xx port d3 timer 2 - channel 2 adc_etr [afr0] 77 61 45 29 pd4/tim2_cc1/b eep i/o x xxhso3xx port d4 timer 2 - channel 1 beep output [afr7] 78 62 46 30 pd5/ linuart_tx i/o x xx o1xx port d5 linuart data transmit 79 63 47 31 pd6/ linuart_rx i/o x xx o1xx port d6 linuart data receive caution: this pin must be held low during power on 80 64 48 32 pd7/tli i/o x xx o1xx port d7 top level interrupt tim1_cc4 [afr4] 1. in the open-drain output column, ?t? defines a true open-drain i/o (p-buffer and protection diode to v dd are not implemented) table 6. stm8a microcontroller family pin description (continued) pin number pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] lqfp80 lqfp64 lqfp48 lqfp32 floating wpu ext. interrupt high sink speed od pp
stm8af61xx, stm8af51xx memory map 33/100 7 memory map figure 7. register and memory map table 7. stack and ram partitioning product kbytes ram size kbytes ram end stack size stack start dec hex 128 6 17ff 1024 0400 1400 up to 2 kbytes data eeprom option and engineering bytes hw registers 2 kbytes rom cpu registers it vectors up to 128 kbytes code flash 00 0000 00 1800 00 4000 00 4800 00 5000 00 5800 00 6000 00 6800 00 7f00 00 8000 02 7fff 00 8080 reserved reserved up to 1 kbyte stack up to 6 kbytes ram 00 4900 reserved
interrupt table stm8af61xx, stm8af51xx 34/100 8 interrupt table table 8. stm8a interrupt table priority source block description interrupt vector address wake-up from halt comments - reset reset 6000h yes reset vector in rom - trap sw interrupt 8004h 0tli external top level interrupt 8008h 1awu auto wake up from halt 800ch yes 2 clock controller main clock controller 8010h 3 misc ext interrupt e0 8014h yes port a interrupts 4 misc ext interrupt e1 8018h yes port b interrupts 5 misc ext interrupt e2 801ch yes port c interrupts 6 misc ext interrupt e3 8020h yes port d interrupts 7 misc ext interrupt e4 8024h yes port e interrupts 8 can can interrupt rx 8028h yes 9can can interrupt tx/er/sc 802ch 10 spi end of transfer 8030h yes 11 timer 1 update/overflow/ trigger/break 8034h 12 timer 1 capture/compare 8038h 13 timer 2 update/overflow/ break 803ch trigger not available on medium end timer 14 timer 2 capture/compare 8040h 15 timer 3 update/overflow/ break 8044h trigger not available on medium end timer 16 timer 3 capture/compare 8048h 17 usart (sci1) tx complete/ er/spi eot/spi error 804ch 18 usart (sci1) receive data full reg. 8050h 19 i 2 c i 2 c interrupts 8054h yes 20 linuart (sci2) tx complete/error/ spi eot/spi error 8058h 21 linuart (sci2) receive data full reg. 805ch
stm8af61xx, stm8af51xx interrupt table 35/100 22 adc end of conversion 8060h 23 timer 4 update/overflow 8064h 24 reserved (1) reserved 8068h 1. also unused interrupts should be initiali zed with ?iret? for robust programming. table 8. stm8a interrupt table (continued) priority source block description interrupt vector address wake-up from halt comments
register mapping stm8af61xx, stm8af51xx 36/100 9 register mapping table 9. stm8a i/o port hardware register map address block register label register name reset status 00 5000h port a pa_odr port a data output latch register 00h 00 5001h pa_idr port a input pin value register 00h 00 5002h pa_ddr port a data direction register 00h 00 5003h pa_cr1 port a control register 1 00h 00 5004h pa_cr2 port a control register 2 00h 00 5005h port b pb_odr port b data output latch register 00h 00 5006h pb_idr port b input pin value register 00h 00 5007h pb_ddr port b data direction register 00h 00 5008h pb_cr1 port b control register 1 00h 00 5009h pb_cr2 port b control register 2 00h 00 500ah port c pc_odr port c data output latch register 00h 00 500bh pc_idr port c input pin value register 00h 00 500ch pc_ddr port c data direction register 00h 00 500dh pc_cr1 port c control register 1 00h 00 500eh pc_cr2 port c control register 2 00h 00 500fh port d pd_odr port d data output latch register 00h 00 5010h pd_idr port d input pin value register 00h 00 5011h pd_ddr port d data direction register 00h 00 5012h pd_cr1 port d control register 1 00h 00 5013h pd_cr2 port d control register 2 00h 00 5014h port e pe_odr port e data output latch register 00h 00 5015h pe_idr port e input pin value register 00h 00 5016h pe_ddr port e data direction register 00h 00 5017h pe_cr1 port e control register 1 00h 00 5018h pe_cr2 port e control register 2 00h 00 5019h port f pf_odr port f data output latch register 00h 00 501ah pf_idr port f input pin value register 00h 00 501bh pf_ddr port f data direction register 00h 00 501ch pf_cr1 port f control register 1 00h 00 501dh pf_cr2 port f control register 2 00h
stm8af61xx, stm8af51xx register mapping 37/100 00 501eh port g pg_odr port g data output latch register 00h 00 501fh pg_idr port g input pin value register 00h 00 5020h pg_ddr port g data direction register 00h 00 5021h pg_cr1 port g control register 1 00h 00 5022h pg_cr2 port g control register 2 00h 00 5023h port h ph_odr port h data output latch register 00h 00 5024h ph_idr port h input pin value register 00h 00 5025h ph_ddr port h data direction register 00h 00 5026h ph_cr1 port h control register 1 00h 00 5027h ph_cr2 port h control register 2 00h 00 5028h port i pi_odr port i data output latch register 00h 00 5029h pi_idr port i input pin value register 00h 00 502ah pi_ddr port i data direction register 00h 00 502bh pi_cr1 port i control register 1 00h 00 502ch pi_cr2 port i control register 2 00h table 9. stm8a i/o port hardware register map (continued) address block register label register name reset status
register mapping stm8af61xx, stm8af51xx 38/100 table 10. stm8a general hardware register map address block register label register name reset status 00 5050h to 00 5059h reserved area (10 bytes) 00 505ah flash flash_cr1 flash control register 1 00h 00 505bh flash_cr2 flash control register 2 00h 00 505ch flash_ncr2 flash complementary control register 2 ffh 00 505dh flash _fpr flash protection register 00h 00 505eh flash _nfpr flash comp lementary protection register ffh 00 505fh flash _iapsr flash in-application programming status register 00h 00 5060h to 00 5061h reserved area (2 bytes) 00 5062h flash flash _pukr flash program memory unprotection register 00h 00 5063h reserved area (1 byte) 00 5064h flash flash _dukr data eeprom unprotection register 00h 00 5065h to 00 509fh reserved area (59 bytes) 00 50a0h itc exti_cr1 external interrupt control register 1 00h 00 50a1h exti_cr2 external interrupt control register 2 00h 00 50a2h to 00 50b2h reserved area (17 bytes) 00 50b3h rst rst_sr reset status register xxh 00 50b4h to 00 50bfh reserved area (12 bytes) 00 50c0h clk clk_ickr internal clock control register 01h 00 50c1h clk_eckr external clock control register 00h 00 50c2h reserved area (1 byte)
stm8af61xx, stm8af51xx register mapping 39/100 00 50c3h clk clk_cmsr clock master status register e1h 00 50c4h clk_swr clock master switch register e1h 00 50c5h clk_swcr clock switch control register xxxx 0000b 00 50c6h clk_ckdivr clock divider register 18h 00 50c7h clk_pckenr1 peripheral clock gating register 1 ffh 00 50c8h clk_cssr clock security system register 00h 00 50c9h clk_ccor configurable clock control register 00h 00 50cah clk_pckenr2 peripheral clock gating register 2 ffh 00 50cbh clk_canccr can clock control register 00h 00 50cch clk_hsitrimr hsi clock calibration trimming register xxh 00 50cdh clk_swimccr swim cl ock control register x0h 00 50ceh to 00 50d0h reserved area (3 bytes) 00 50d1h wwdg wwdg_cr wwdg control register 7fh 00 50d2h wwdg_wr wwdr window register 7fh 00 50d3h to 00 50dfh reserved area (13 bytes) 00 50e0h iwdg iwdg_kr iwdg key register - 00 50e1h iwdg_pr iwdg prescaler register 00h 00 50e2h iwdg_rlr iwdg reload register ffh 00 50e3h to 00 50efh reserved area (13 bytes) 00 50f0h awu awu_csr1 awu control/status register 1 00h 00 50f1h awu_apr awu asynchronous prescaler buffer register 3fh 00 50f2h awu_tbr awu timebase selection register 00h 00 50f3h beep beep_csr beep cont rol/status register 1fh 00 50f4h to 00 50ffh reserved area (12 bytes) table 10. stm8a general hardware register map (continued) address block register label register name reset status
register mapping stm8af61xx, stm8af51xx 40/100 00 5200h spi spi_cr1 spi control register 1 00h 00 5201h spi_cr2 spi control register 2 00h 00 5202h spi_icr spi interrupt control register 00h 00 5203h spi_sr spi status register 02h 00 5204h spi_dr spi data register 00h 00 5205h spi_crcpr spi crc polynomial register 07h 00 5206h spi_rxcrcr spi rx crc register ffh 00 5207h spi_txcrcr spi tx crc register ffh 00 5208h to 00 520fh reserved area (8 bytes) 00 5210h i 2 c i2c_cr1 i 2 c control register 1 00h 00 5211h i2c_cr2 i 2 c control register 2 00h 00 5212h i2c_freqr i 2 c frequency register 00h 00 5213h i2c_oarl i 2 c own address register low 00h 00 5214h i2c_oarh i 2 c own address register high 00h 00 5215h reserved 00 5216h i2c_dr i 2 c data register 00h 00 5217h i2c_sr1 i 2 c status register 1 00h 00 5218h i2c_sr2 i 2 c status register 2 00h 00 5219h i2c_sr3 i 2 c status register 3 00h 00 521ah i2c_itr i 2 c interrupt control register 00h 00 521bh i2c_ccrl i 2 c clock control register low 00h 00 521ch i2c_ccrh i 2 c clock control register high 00h 00 521dh i2c_triser i 2 c trise register 02h 00 521eh i2c_pecr i 2 c packet error checking register 00h 00 521fh to 00 522fh reserved area (17 bytes) table 10. stm8a general hardware register map (continued) address block register label register name reset status
stm8af61xx, stm8af51xx register mapping 41/100 00 5230h usart usart_sr usart status register c0h 00 5231h usart_dr usart data register xxh 00 5232h usart_brr1 usart baud rate register 1 00h 00 5233h usart_brr2 usart baud rate register 2 00h 00 5234h usart_cr1 usart control register 1 00h 00 5235h usart_cr2 usart control register 2 00h 00 5236h usart_cr3 usart control register 3 00h 00 5237h usart_cr4 usart control register 4 00h 00 5238h usart_cr5 usart control register 5 00h 00 5239h usart_gtr usart guard time register 00h 00 523ah usart_pscr usart prescaler register 00h 00 523bh to 00 523fh reserved area (5 bytes) 00 5240h linuart linuart_sr linuart status register c0h 00 5241h linuart_dr linuart data register xxh 00 5242h linuart_brr1 linuart baud rate register 1 00h 00 5243h linuart_brr2 linuart baud rate register 2 00h 00 5244h linuart_cr1 linuart control register 1 00h 00 5245h linuart_cr2 linuart control register 2 00h 00 5246h linuart_cr3 linuart control register 3 00h 005247h linuart_cr4 linuart control register 4 00h 00 5248h reserved 00 5249h linuart_cr6 linuart control register 6 00h 00 524ah to 00 524fh reserved area (6 bytes) table 10. stm8a general hardware register map (continued) address block register label register name reset status
register mapping stm8af61xx, stm8af51xx 42/100 00 5250h tim1 tim1_cr1 tim1 control register 1 00h 00 5251h tim1_cr2 tim1 control register 2 00h 00 5252h tim1_smcr tim1 slave mode control register 00h 00 5253h tim1_etr tim1 external trigger register 00h 00 5254h tim1_ier tim1 interrupt enable register 00h 00 5255h tim1_sr1 tim1 st atus register 1 00h 00 5256h tim1_sr2 tim1 st atus register 2 00h 00 5257h tim1_egr tim1 event generation register 00h 00 5258h tim1_ccmr1 tim1 capture/compare mode register 1 00h 00 5259h tim1_ccmr2 tim1 capture/compare mode register 2 00h 00 525ah tim1_ccmr3 tim1 capture/compare mode register 3 00h 00 525bh tim1_ccmr4 tim1 capture/compare mode register 4 00h 00 525ch tim1_ccer1 tim1 capture/compare enable register 1 00h 00 525dh tim1_ccer2 tim1 capture/compare enable register 2 00h 00 525eh tim1_cntrh tim1 counter high 00h 00 525fh tim1_cntrl tim1 counter low 00h 00 5260h tim1_pscrh tim1 prescaler register high 00h 00 5261h tim1_pscrl tim1 prescaler register low 00h 00 5262h tim1_arrh tim1 auto-reload register high ffh 00 5263h tim1_arrl tim1 auto-reload register low ffh 00 5264h tim1_rcr tim1 repetition counter register 00h 00 5265h tim1_ccr1h tim1 capture/compare register 1 high 00h 00 5266h tim1_ccr1l tim1 capture/compare register 1 low 00h 00 5267h tim1_ccr2h tim1 capture/compare register 2 high 00h 00 5268h tim1_ccr2l tim1 capture/compare register 2 low 00h 00 5269h tim1_ccr3h tim1 capture/compare register 3 high 00h 00 526ah tim1_ccr3l tim1 capture/compare register 3 low 00h 00 526bh tim1_ccr4h tim1 capture/compare register 4 high 00h 00 526ch tim1_ccr4l tim1 capture/compare register 4 low 00h 00 526dh tim1_bkr tim1 break register 00h 00 526eh tim1_dtr tim1 dead-time register 00h 00 526fh tim1_oisr tim1 output idle state register 00h 00 5270h to 00 52ffh reserved area (147 bytes) table 10. stm8a general hardware register map (continued) address block register label register name reset status
stm8af61xx, stm8af51xx register mapping 43/100 00 5300h tim2 tim2_cr1 tim2 control register 1 00h 00 5301h tim2_ier tim2 interrupt enable register 00h 00 5302h tim2_sr1 tim2 st atus register 1 00h 00 5303h tim2_sr2 tim2 st atus register 2 00h 00 5304h tim2_egr tim2 event generation register 00h 00 5305h tim2_ccmr1 tim2 capture/compare mode register 1 00h 00 5306h tim2_ccmr2 tim2 capture/compare mode register 2 00h 00 5307h tim2_ccmr3 tim2 capture/compare mode register 3 00h 00 5308h tim2_ccer1 tim2 capture/compare enable register 1 00h 00 5309h tim2_ccer2 tim2 capture/compare enable register 2 00h 00 530ah tim2_cntrh tim2 counter high 00h 00 530bh tim2_cntrl tim2 counter low 00h 00 530ch tim2_pscr tim2 prescaler register 00h 00 530dh tim2_arrh tim2 auto-reload register high ffh 00 530eh tim2_arrl tim2 auto-reload register low ffh 00 530fh tim2_ccr1h tim2 captur e/compare register 1 high 00h 00 5310h tim2_ccr1l tim2 capture/compare register 1 low 00h 00 5311h tim2_ccr2h tim2 capture/compare register 2 high 00h 00 5312h tim2_ccr2l tim2 capture/compare register 2 low 00h 00 5313h tim2_ccr3h tim2 capture/compare register 3 high 00h 00 5314h tim2_ccr3l tim2 capture/compare register 3 low 00h 00 5315h to 00 531fh reserved area (11 bytes) table 10. stm8a general hardware register map (continued) address block register label register name reset status
register mapping stm8af61xx, stm8af51xx 44/100 00 5320h tim3 tim3_cr1 tim3 control register 1 00h 00 5321h tim3_ier tim3 interrupt enable register 00h 00 5322h tim3_sr1 tim3 st atus register 1 00h 00 5323h tim3_sr2 tim3 st atus register 2 00h 00 5324h tim3_egr tim3 event generation register 00h 00 5325h tim3_ccmr1 tim3 capture/compare mode register 1 00h 00 5326h tim3_ccmr2 tim3 capture/compare mode register 2 00h 00 5327h tim3_ccer1 tim3 capture/compare enable register 1 00h 00 5328h tim3_cntrh tim3 counter high 00h 00 5329h tim3_cntrl tim3 counter low 00h 00 532ah tim3_pscr tim3 prescaler register 00h 00 532bh tim3_arrh tim3 aut o-reload register high ffh 00 532ch tim3_arrl tim3 auto-reload register low ffh 00 532dh tim3_ccr1h tim3 capture/compare register 1 high 00h 00 532eh tim3_ccr1l tim3 capture/compare register 1 low 00h 00 532fh tim3_ccr2h tim3 captur e/compare register 2 high 00h 00 5330h tim3_ccr2l tim3 capture/compare register 2 low 00h 00 5331h to 00 533fh reserved area (15 bytes) 00 5340h tim4 tim4_cr1 tim4 control register 1 00h 00 5341h tim4_ier tim4 interrupt enable register 00h 00 5342h tim4_sr tim4 status register 00h 00 5343h tim4_egr tim4 event generation register 00h 00 5344h tim4_cntr tim4 counter 00h 00 5345h tim4_pscr tim4 prescaler register 00h 00 5346h tim4_arr tim4 auto-reload register ffh 00 5347h to 00 53ffh reserved area (184 bytes) table 10. stm8a general hardware register map (continued) address block register label register name reset status
stm8af61xx, stm8af51xx register mapping 45/100 00 5400h adc adc _csr adc control/ status register 00h 00 5401h adc_cr1 adc configuration register 1 00h 00 5402h adc_cr2 adc configuration register 2 00h 00 5403h adc_cr3 adc configuration register 3 00h 00 5404h adc_drh adc data register high 00h 00 5405h adc_drl adc data register low 00h 00 5406h adc_tdrh adc schmitt trigger disable register high 00h 00 5407h adc_tdrl adc schmitt trigger disable register low 00h 00 5408h to 00 541fh reserved area (24 bytes) 00 5420h can can_mcr can master control register 02h 00 5421h can_msr can master status register 02h 00 5422h can_tsr can transmit status register 00h 00 5423h can_tpr can transmit priority register 0ch 00 5424h can_rfr can receive fifo register 00h 00 5425h can_ier can interrupt enable register 00h 00 5426h can_dgr can diagnosis register 0ch 00 5427h can_fpsr can page selection register 00h 00 5428h can_p0 can paged register 0 00h 00 5429h can_p1 can paged register 1 00h 00 542ah can_p2 can paged register 2 00h 00 542bh can_p3 can paged register 3 00h 00 542ch can_p4 can paged register 4 00h 00 542dh can_p5 can paged register 5 00h 00 542eh can_p6 can paged register 6 00h 00 542fh can_p7 can paged register 7 00h 00 5430h can_p8 can paged register 8 00h 00 5431h can_p9 can paged register 9 00h 00 5432h can_pa can paged register a 00h 00 5433h can_pb can paged register b 00h 00 5434h can_pc can paged register c 00h 00 5435h can_pd can paged register d 00h 00 5436h can_pe can paged register e 00h 00 5437h can_pf can paged register f 00h table 10. stm8a general hardware register map (continued) address block register label register name reset status
register mapping stm8af61xx, stm8af51xx 46/100 00 5438h to 00 57ffh reserved area (968 bytes) 5800h tmu tu_keys_reg0 tmu key register 1 [7:0] 00h 5801h tu_keys_reg1 tmu key register 2 [7:0] 00h 5802h tu_keys_reg2 tmu key register 3 [7:0] 00h 5803h tu_keys_reg3 tmu key register 4 [7:0] 00h 5804h tu_keys_reg4 tmu key register 5 [7:0] 00h 5805h tu_keys_reg5 tmu key register 6 [7:0]] 00h 5806h tu_keys_reg6 tmu key register 7 [7:0] 00h 5807h tu_keys_reg7 tmu key register 8 [7:0] 00h 5808h tu_ctl_st tmu control and status register 00h table 10. stm8a general hardware register map (continued) address block register label register name reset status
stm8af61xx, stm8af51xx register mapping 47/100 table 11. cpu/swim/debug module/interrupt controller registers address block register label register name reset status 00 7f00h cpu a accumulator 00h 00 7f01h pce program counter extended 00h 00 7f02h pch program counter high 60h 00 7f03h pcl program counter low 00h 00 7f04h xh x index register high 00h 00 7f05h xl x index register low 00h 00 7f06h yh y index register high 00h 00 7f07h yl y index register low 00h 00 7f08h sph stack pointer high 17h 00 7f09h spl stack pointer low ffh 00 7f0ah ccr condition code register 28h 00 7f0bh to 00 7f5fh reserved area (85 bytes) 00 7f60h cfg cfg_gcr global configuration register 00h 00 7f70h itc itc_spr1 interrupt software priority register 1 ffh 00 7f71h itc_spr2 interrupt software priority register 2 ffh 00 7f72h itc_spr3 interrupt software priority register 3 ffh 00 7f73h itc_spr4 interrupt software priority register 4 ffh 00 7f74h itc_spr5 interrupt software priority register 5 ffh 00 7f75h itc_spr6 interrupt software priority register 6 ffh 00 7f76h itc_spr7 interrupt software priority register 7 ffh 00 7f77h to 00 7f79h reserved area (3 bytes) 00 7f80h swim swim_csr swim control status register 00h 00 7f81h to 00 7f8fh reserved area (15 bytes)
register mapping stm8af61xx, stm8af51xx 48/100 00 7f90h dm dm_bk1re dm breakpoint 1 register extended byte ffh 00 7f91h dm_bk1rh dm breakpoint 1 register high byte ffh 00 7f92h dm_bk1rl dm breakpoint 1 register low byte ffh 00 7f93h dm_bk2re dm breakpoint 2 register extended byte ffh 00 7f94h dm_bk2rh dm breakpoint 2 register high byte ffh 00 7f95h dm_bk2rl dm breakpoint 2 register low byte ffh 00 7f96h dm_cr1 debug module control register 1 00h 00 7f97h dm_cr2 debug module control register 2 00h 00 7f98h dm_csr1 debug module control/status register 1 10h 00 7f99h dm_csr2 debug module control/status register 2 00h 00 7f9ah dm_enfctr dm enable function register ffh 00 7f9bh to 00 7f9fh reserved area (5 bytes) table 11. cpu/swim/debug module/interrupt controller registers (continued) address block register label register name reset status
stm8af61xx, stm8af51xx option bytes 49/100 10 option bytes option bytes contain configurations for device hardware features as well as the memory protection of the device. they are stored in a dedicated block of the memory. each option byte has to be stored twice, for redundancy, in a regular form (optx) and a complemented one (noptx), except for the rop (read-out protection) option byte and option bytes 8 to 16. option bytes can be modified in icp mode (via swim) by accessing the eeprom address shown in table 12: option bytes below. option bytes can also be modified ?on the fly? by the application in iap mode, except the rop and ubc options that can only be toggled in icp mode (via swim). refer to the stm8 flash programming manual (pm0047) and stm8 swim communication protocol and debug modulel user manual (um0470) for information on swim programming procedures. table 12. option bytes addr. option name option byte no. option bits factory default setting 765 4 3 2 1 0 4800h read-out protection (rop) opt0 rop[7:0] 00h 4801h user boot code (ubc) opt1 ubc[7:0] 00h 4802h nopt1 nubc[7:0] ffh 4803h alternate function remappin g (afr) opt2 afr7 afr6 afr5 afr4 afr3 afr2 afr1 afr0 00h 4804h nopt2 nafr 7 nafr 6 nafr5 nafr4 nafr3 nafr2 nafr1 nafr0 ffh 4805h watchdog option opt3 reserved lsi _en iwdg _hw wwdg _hw wwdg _halt 00h 4806h nopt3 reserved nlsi _en niwdg _hw nwwd g_hw nwwg _halt ffh 4807h clock option opt4 reserved ext clk ckawu sel prs c1 prs c0 00h 4808h nopt4 reserved next clk nckaw usel npr sc1 npr sc0 ffh 4809h hse clock startup opt5 hsecnt[7:0] 00h 480ah nopt5 nhsecnt[7:0] ffh 480bh tmu opt6 tmu[3:0] 00h 480ch nopt6 ntmu[3:0] ffh 480dh flash wait states opt7 reserved wait state 00h 480eh nopt7 reserved nwait state ffh 480fh reserved
option bytes stm8af61xx, stm8af51xx 50/100 4810h tmu opt8 tmu_key 1 [7:0] 00h 4811h opt9 tmu_key 2 [7:0] 00h 4812h opt10 tmu_key 3 [7:0] 00h 4813h opt11 tmu_key 4 [7:0] 00h 4814h opt12 tmu_key 5 [7:0] 00h 4815h opt13 tmu_key 6 [7:0] 00h 4816h opt14 tmu_key 7 [7:0] 00h 4817h opt15 tmu_key 8 [7:0] 00h 4818h opt16 tmu max_att [7:0] 00h 4819h to 487d reserved 487e boot- loader opt17 bl_en [7:0] 00h 487f nopt17 nbl_en [7:0] 00h table 12. option bytes (continued) addr. option name option byte no. option bits factory default setting 765 4 3 2 1 0
stm8af61xx, stm8af51xx option bytes 51/100 table 13. option byte description option byte no. description opt0 rop[7:0]: memory readout protection (rop) aah: enable readout protection (w rite access via swim protocol) note: refer to the stm8a microcontroller family reference manual (rm0009) section on flash/eeprom memory readout protection for details. opt1 ubc[7:0]: user boot code area 00h: no ubc, no write-protection 01h: page 0 to 1 defined as ubc, memory write-protected 02h: page 0 to 3 defined as ubc, memory write-protected 03h to ffh: pages 4 to 255 defined as ubc, memory write-protected note: refer to the stm8a microcontroller family reference manual (rm0009) section on flash/eeprom wr ite protection for more details. opt2 afr7: alternate function remapping option 7 0: port d4 alternate function = tim2_cc1 1: port d4 alternate function = beep afr6: alternate function remapping option 6 0: port b5 alternate function = ai n5, port b4 alternate function = ain4 1: port b5 alternate function = i 2 c_sda, port b4 alternate function = i 2 c_scl. afr5: alternate function remapping option 5 0: port b3 alternate function = ai n3, port b2 alternate function = ain2, port b1 alternate function = ain1, port b0 alternate function = ain0. 1: port b3 alternate function = ti m1_etr, port b2 alternate function = tim1_ncc3, port b1 alternate func tion = tim1_ncc2, port b0 alternate function = tim1_ncc1. afr4: alternate function remapping option 4 0: port d7 alternate function = tli 1: port d7 alternate function = tim1_cc4 afr3: alternate function remapping option 3 0: port d0 alternate function = tim3_cc2 1: port d0 alternate function = tim1_bkin afr2: alternate function remapping option 2 0: port d0 alternate function = tim3_cc2 1: port d0 alternate function = clk_cco note: afr2 option has priority over afr3 if both are activated afr1: alternate function remapping option 1 0: port a3 alternate function = ti m2_cc3, port d2 alternate function tim3_cc1. 1: port a3 alternate function = ti m3_cc1, port d2 alternate function tim2_cc3. afr0: alternate function remapping option 0 0: port d3 alternate function = tim2_cc2 1: port d3 alternate function = adc_etr
option bytes stm8af61xx, stm8af51xx 52/100 opt3 lsi_en: low speed internal clock enable 0: lsi clock is not available as cpu clock source 1: lsi clock is available as cpu clock source iwdg_hw: independent watchdog 0: iwdg independent watchdog activated by software 1: iwdg independent watchdog activated by hardware wwdg_hw: window watchdog activation 0: wwdg window watchdog activated by software 1: wwdg window watchdog activated by hardware wwdg_halt: window watchdog reset on halt 0: no reset generated on halt if wwdg active 1: reset generated on halt if wwdg active opt4 extclk: external clock selection 0: external crystal c onnected to oscin/oscout 1: external clock signal on oscin ckawusel: auto wake-up unit/clock 0: lsi clock source selected for awu 1: hse clock with prescaler selected as clock source for for awu prsc[1:0]: awu clock prescaler 00: 24 mhz to 128 khz prescaler 01: 16 mhz to 128 khz prescaler 10: 8 mhz to 128 khz prescaler 11: 4 mhz to 128 khz prescaler opt5 hsecnt[7:0]: hse crystal oscillator stabilization time this configures the stabilisation ti me to 0.5, 8, 128, and 2048 hse cycles with corresponding option byte values of e1h, d2h, b4h, and 00h. opt6 tmu[3:0]: enable temporary memory unprotection 0101: tmu disabled (permanent rop). any other value: tmu enabled. opt7 wait state: wait state configuration this option configures the number of wait states inserted when reading from the flash/data eeprom memory. 0: no wait state 1: one wait state opt8 tmu_key 1 [7:0]: temporary unprotection key 0 temporary unprotection key: must be different from 00h or ffh opt9 tmu_key 2 [7:0]: temporary unprotection key 1 temporary unprotection key: must be different from 00h or ffh opt10 tmu_key 3 [7:0]: temporary unprotection key 2 temporary unprotection key: must be different from 00h or ffh opt11 tmu_key 4 [7:0]: temporary unprotection key 3 temporary unprotection key: must be different from 00h or ffh table 13. option byte description (continued) option byte no. description
stm8af61xx, stm8af51xx option bytes 53/100 opt12 tmu_key 5 [7:0]: temporary unprotection key 4 temporary unprotection key: must be different from 00h or ffh opt13 tmu_key 6 [7:0]: temporary unprotection key 5 temporary unprotection key: must be different from 00h or ffh opt14 tmu_key 7 [7:0]: temporary unprotection key 6 temporary unprotection key: must be different from 00h or ffh opt15 tmu_key 8 [7:0]: temporary unprotection key 7 temporary unprotection key: must be different from 00h or ffh opt16 tmu_maxatt [7:0]: tmu access failure counter every unsuccessful trial to enter t he temporary unprotection procedure increments the counter. more than ei ght unsuccessful trials trigger the global erase of the code and data memory. opt17 bl_en [7:0]: bootloader enable if this optionbyte is set to 55h (compl ementary value aah) the bootloader program is activated also in case of a programmed code memory (for more details, see the bootloader user manual, um0500). table 13. option byte description (continued) option byte no. description
electrical characteristics stm8af61xx, stm8af51xx 54/100 11 electrical characteristics 11.1 parameter conditions unless otherwise specified, all voltages are referred to v ss . 11.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100 % of the devices with an ambient temperature at t a = 25 c and t a = t amax (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. 11.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 5.0 v. they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range . 11.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 11.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 8 . figure 8. pin loading conditions 50 pf stm8a pin
stm8af61xx, stm8af51xx electrical characteristics 55/100 11.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 9 . figure 9. pin input voltage 11.2 absolute maximum ratings stresses above those listed as ?absolute ma ximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. v in stm8a pin table 14. voltage characteristics symbol ratings min max unit v ddx - v ss supply voltage (including v dda and v ddio ) (1) 1. all power (v dd , v ddio , v dda ) and ground (v ss , v ssio , v ssa ) pins must always be connected to the external power supply -0.3 6.5 v v in input voltage on true open drain pins (pe1, pe2) (2) 2. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in > v dd while a negative injection is induced by v in < v ss . for true open-drain pads, there is no positive injection current, and the corresponding v in maximum must always be respected v ss - 0.3 6.5 input voltage on any other pin (2) v ss - 0.3 v dd + 0.3 |v ddx - v ss | variations between different power pins 50 mv |v ssx - v ss | variations between all the different ground pins 50 v esd electrostatic discharge voltage see absolute maximum ratings (electrical sensitivity) on page 86
electrical characteristics stm8af61xx, stm8af51xx 56/100 table 15. current characteristics symbol ratings max. unit i vdd total current into v dd power lines (source) (1)(2) 1. all power (v dd , v ddio , v dda ) and ground (v ss , v ssio , v ssa ) pins must always be connected to the external supply. 2. the total limit applies to the sum of operation and injected currents. 60 ma i vss total current out of v ss ground lines (sink) (1)(2) 60 i io output current sunk by any i/o and control pin 20 output current source by any i/os and control pin - 20 i inj(pin) (3) 3. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in > v dd while a negative injection is induced by v in < v ss . for true open-drain pads, there is no positive injection cu rrent allowed and the corresponding v in maximum must always be respected. injected current on nrst pin 10 injected current on oscin pin 10 injected current on any other pin 10 i inj(pin) (4) 4. when several inputs are submitted to a current injection, the maximum i inj(pin) is the sum of the absolute positive and negative injected currents (insta ntaneous values). thes e results are based on characterization with i inj(pin) maximum current injection on four i/o port pins of the device. total injected current (sum of all i/o and control pins) 20 table 16. thermal characteristics symbol ratings value unit t stg storage temperature range -65 to +150 c t j maximum junction temperature 150
stm8af61xx, stm8af51xx electrical characteristics 57/100 11.3 operating conditions figure 10. f cpumax versus v dd table 17. general operating conditions symbol parameter co nditions min max unit f cpu internal cpu clock frequency t a 105 c 0 24 mhz t a > 105 c 0 16 v dd/ v dd_io standard operating voltage 3.0 5.5 v t a ambient temperature suffix a -40 85 c suffix b -40 105 c suffix c -40 125 c suffix d -40 145 c t j junction temperature range a suffix version -40 90 c b suffix version -40 110 c c suffix version -40 130 c d suffix version -40 150 c f cpu [mhz] supply voltage [v] 24 12 8 4 0 3.0 4.0 5.0 functionality functionality guaranteed @ t a -40 to 125 ? not guaranteed in this area 16 5.5 functionality guaranteed @ t a -40 to 105 ?
electrical characteristics stm8af61xx, stm8af51xx 58/100 11.3.1 supply current characteristics the current consumption is measured as described in figure 8 on page 54 and figure 9 on page 55 . total current consumption the mcu is placed under the following conditions: all i/o pins in input mode with a static value at v dd or v ss (no load) all peripherals are disabled exce pt if explicitly mentioned. subject to general operating conditions for v dd and t a . note on the run-current typical and worst-case values typical device currents values are representative of an application set-up without any i/o activity at 25 c. the worst case values correspond to the actual test-limits and include both internal and external device i/o current. during the execution of an actual application program, the number of read access cycles to the code memory depends on its structure. a code doing arithmetical calculations reads the memory less frequently than programs with jump, loop or data manipulation instructions. the fast-reading access in a flash memory needs much more power compared to a ram. cons equently, the run- current for eeprom execution depends strongly on the actual application code structure. the measurements in the tables below were made using a short, representative code with move, jump and arithmetic operations. the worst case, an infinite loop of ?while? instructions takes approximately 25 % more power. for ram execution, such power to program structure relations has not been observed. table 18. operating conditions at power-up/power-down symbol parameter conditions min typ max unit t vdd v dd rise time rate 20 (1) 1. guaranteed by design, not tested in production s/v v dd fall time rate (3) 20 (2) 2. tbd = to be determined t temp reset release delay v dd rising tbd (2) 3ms reset generation delay (3) 3. reset is always generated after a t temp delay. the application must ensure that v dd is still above the minimum operating voltage (v dd min) when the t temp delay has elapsed. v dd falling tbd (2) 3s v it+ power-on reset threshold 2.65 2.8 2.95 v v it- brown-out reset threshold 2.58 2.73 2.88 v v hys(bor) brown-out reset hysteresis 70 (1) mv
stm8af61xx, stm8af51xx electrical characteristics 59/100 table 19. total current consumption in run, wait and slow mode at v dd = 5.0 v symbol parameter conditions typ max unit i dd(run) supply current in run mode all peripherals off, code executed from ram hse crystal oscillator f cpu = f master = 24 mhz 4.4 ma hse external clock f cpu = f master = 24 mhz 3.8 hse crystal oscillator f cpu = f master = 16 mhz 3.3 hse external clock f cpu = f master = 16 mhz 2.7 6.0 (1) hsi internal rc f cpu = f master = 16 mhz 2.55 hsi internal rc 16 mhz/8 f cpu = f master = 2 mhz 1.2 i dd(run) supply current in run mode all peripherals off, code executed from eeprom hse crystal oscillator f cpu = f master = 24 mhz 11.4 ma hse external clock f cpu = f master = 24 mhz 10.8 hse crystal oscillator f cpu = f master = 16 mhz 9.0 hse external clock f cpu = f master = 16 mhz 8.35 15.0 (1) hsi internal rc f cpu = f master = 16 mhz 8.2 hsi internal rc 16 mhz/8 f cpu = f master = 2 mhz 1.9 i dd(run) supply current in run mode all peripherals on, code executed from ram hse crystal oscillator f cpu = f master = 24 mhz 6.9 ma hse external clock f cpu = f master = 24 mhz 6.3 hse crystal oscillator f cpu = f master = 16 mhz 4.3 hse external clock f cpu = f master = 16 mhz 3.7 8.0 (1) hsi internal rc f cpu = f master = 16 mhz 3.5 hsi internal rc 16 mhz/8 f cpu = f master = 2 mhz 1.2
electrical characteristics stm8af61xx, stm8af51xx 60/100 i dd(run) supply current in run mode all peripherals on, code executed from eeprom hse crystal oscillator f cpu = f master = 24 mhz 13.9 ma hse external clock f cpu = f master = 24 mhz 13.3 hse crystal oscillator f cpu = f master = 16 mhz 10.0 hse external clock f cpu = f master = 16 mhz 9.35 hsi internal rc f cpu = f master = 16 mhz 9.2 hsi internal rc 16 mhz/8 f cpu = f master = 2 mhz 2.1 i dd(wfi) supply current in wait mode cpu not clocked, all peripherals off hse crystal oscillator f cpu = f master = 24 mhz 2.4 ma hse external clock f cpu = f master = 24 mhz 1.8 hse crystal oscillator f cpu = f master = 16 mhz 2.0 hse external clock f cpu = f master = 16 mhz 1.38 4.0 (1) hsi internal rc f cpu = f master = 16 mhz 1.21 hsi internal rc 16 mhz/8 f cpu = f master = 2 mhz 1.05 i dd(slow) supply current in slow mode f cpu scaled down, all peripherals off, code executed from ram hse external clock 16 mhz/128 f cpu = f master = 0.125 mhz 1.15 4.0 (1) ma hsi internal rc 16 mhz/128 f cpu = f master = 0.125 mhz 1.04 lsi internal rc 128 khz f cpu = f master = 0.128 mhz 0.5 f cpu scaled down, all peripherals off, code executed from eeprom hse external clock 16 mhz/128 f cpu = f master = 0.125 mhz 1.21 hsi internal rc 16 mhz/128 f cpu = f master = 0.125 mhz 1.09 lsi internal rc 128 khz f cpu = f master = 0.128 mhz 0.56 1. prodution test limits table 19. total current consumption in run, wait and slow mode at v dd = 5.0 v symbol parameter conditions typ max unit
stm8af61xx, stm8af51xx electrical characteristics 61/100 table 20. total current consumption and timing in halt, fast active halt and slow active halt modes at v dd = 5.0 v symbol parameter conditions typ max unit i dd(h) supply current in halt mode flash powered down 6.5 10 (1) 1. maximum values at 55 c, tested in production ac cording to the actual product temperature ranges. a flash in stand-by mode 64 i dd(fah) supply current in fast active halt mode crystal osc 16 mhz/128 1050 hse osc 16 mhz/128 490 lsi rc 128 khz 150 200 (1) i dd(sah) supply current in slow active halt mode lsi rc 128 khz 11 30 (1) t wu(fah) wake-up time from fast active halt mode to run mode 2 (2) 2. data based on characterization results, not tested in production. s t wu(sah) wake-up time from slow active halt mode to run mode 100 (2) table 21. total current consumption in run, wait and slow mode at v dd = 3.3 v symbol parameter conditions typ max unit i dd(run) supply current in run mode all peripherals off, code executed from ram hse crystal oscillator f cpu = f master = 24 mhz 4 ma hse external clock f cpu = f master = 24 mhz 3.8 hse crystal oscillator f cpu = f master = 16 mhz 2.9 hse external clock f cpu = f master = 16 mhz 2.7 hsi internal rc f cpu = f master = 16 mhz 2.55 hsi internal rc 16 mhz/8 f cpu = f master = 2 mhz 1.2
electrical characteristics stm8af61xx, stm8af51xx 62/100 i dd(run) supply current in run mode all peripherals off, code executed from eeprom hse crystal oscillator f cpu = f master = 24 mhz 11.0 ma hse external clock f cpu = f master = 24 mhz 10.8 hse crystal oscillator f cpu = f master = 16 mhz 8.6 hse external clock f cpu = f master = 16 mhz 8.35 hsi internal rc f cpu = f master = 16 mhz 8.2 hsi internal rc 16 mhz/8 f cpu = f master = 2 mhz 1.6 i dd(run) supply current in run mode all peripherals on, code executed from ram hse crystal oscillator f cpu = f master = 24 mhz 6.5 ma hse external clock f cpu = f master = 24 mhz 6.3 hse crystal oscillator f cpu = f master = 16 mhz 3.9 hse external clock f cpu = f master = 16 mhz 3.7 hsi internal rc f cpu = f master = 16 mhz 3.55 hsi internal rc 16 mhz/8 f cpu = f master = 2 mhz 1.4 i dd(run) supply current in run mode all peripherals on, code executed from eeprom hse crystal oscillator f cpu = f master = 24 mhz 13.5 ma hse external clock f cpu = f master = 24 mhz 13.3 hse crystal oscillator f cpu = f master = 16 mhz 9.6 hse external clock f cpu = f master = 16 mhz 9.35 hsi internal rc f cpu = f master = 16 mhz 9.2 hsi internal rc 16 mhz/8 f cpu = f master = 2 mhz 1.8 table 21. total current consumption in run, wait and slow mode at v dd = 3.3 v symbol parameter conditions typ max unit
stm8af61xx, stm8af51xx electrical characteristics 63/100 i dd(wfi) supply current in wait mode cpu not clocked, all peripherals off hse crystal oscillator f cpu = f master = 24 mhz 2.0 ma hse external clock f cpu = f master = 24 mhz 1.8 hse crystal oscillator f cpu = f master = 16 mhz 1.6 hse external clock f cpu = f master = 16 mhz 1.38 hsi internal rc f cpu = f master = 16 mhz 1.21 hsi internal rc 16 mhz/8 f cpu = f master = 2 mhz 1.05 i dd(slow) supply current in slow mode f cpu scaled down, all peripherals off, code executed from ram hse external clock 16 mhz/128 f cpu = f master = 0.125 mhz 1.15 ma hsi internal rc 16 mhz/128 f cpu = f master = 0.125 mhz 1.04 lsi internal rc 128 khz f cpu = f master = 0.128mhz 0.5 f cpu scaled down, all peripherals off, code executed from eeprom hse external clock 16 mhz/128 f cpu = f master = 0.125 mhz 1.21 hsi internal rc 16 mhz/128 f cpu = f master = 0.125 mhz 1.09 lsi internal rc 128 khz f cpu = f master = 0.128 mhz 0.56 table 21. total current consumption in run, wait and slow mode at v dd = 3.3 v symbol parameter conditions typ max unit
electrical characteristics stm8af61xx, stm8af51xx 64/100 table 22. total current consumption and timing in halt, fast active halt and slow active halt modes at v dd = 3.3 v symbol parameter conditions typ max unit i dd(h) supply current in halt mode flash powered down 4.7 a flash in stand-by mode 62 i dd(fah) supply current in fast active halt mode crystal osc 16 mhz/128 600 hse osc 16 mhz/128 490 lsi rc 128 khz 140 i dd(sah) supply current in slow active halt mode lsi rc 128 khz 9 t wu(fah) wake-up time from fast active halt mode to run mode 2 (1) 1. data based on characterization results, not tested in production s t wu(sah) wake-up time from slow active halt mode to run mode 100 (1)
stm8af61xx, stm8af51xx electrical characteristics 65/100 on-chip peripherals table 23. typical peripheral current consumption v dd = 5.0 v (1) 1. typical values - not tested in production. since the peripherals are powered by an internally regulated, constant digital supply voltage, the values are similar in the full supply voltage range. symbol parameter typ. f master = 2 mhz typ. f master = 16 mhz typ. f master = 24 mhz unit i dd(tim1) tim1 supply current (2) 2. data based on a differential i dd measurement between no peripheral clocked and a single active peripheral. this measurement does not include the pad toggling consumption. 0.03 0.23 0.34 ma i dd(tim2) tim2 supply current (2) 0.02 0.12 0.19 i dd(tim3) tim3 supply current (2) 0.01 0.1 0.16 i dd(tim4) tim4 supply current (2) 0.004 0.03 0.05 i dd(usart) usart supply current (2) 0.03 0.09 0.15 i dd(linuart) linuart supply current (2) 0.03 0.11 0.18 i dd(spi) spi supply current (2) 0.01 0.04 0.07 i dd(i 2 c) i 2 c supply current (2) 0.02 0.06 0.91 i dd(can) can supply current (3) 3. data based on a differential idd measurement between reset configuration (can disabled) and a permanent can data transmit sequence in loopback m ode at 1 mhz. this measurement does not include the pad toggling consumption. 0.06 0.22 0.34 i dd(awu) awu supply current (2) 0.003 0.02 0.05 i dd(tot_dig) all digital peripherals on 0.22 1 2.4 i dd(adc) adc supply current when converting (4) 4. data based on a differential i dd measurement between reset configuration and continuous a/d conversions. 0.93 0.95 0.96 i dd(ee_prog) data eeprom programming current 2.5 2.9 3.1
electrical characteristics stm8af61xx, stm8af51xx 66/100 current consumption curves figure 11 to figure 16 show typical current consumption measured with code executing in ram. figure 11. typ. i dd(run)hse vs. v dd @f cpu = 16 mhz, periph = on figure 12. typ. i dd(run)hse vs. f cpu @v dd = 5.0 v, periph = on 0 1 2 3 4 5 6 7 8 9 10 2.533.544.555.56 v dd [v] i dd(run)hse [ma] 25c 85c 12 5 c 0 1 2 3 4 5 6 7 8 9 10 0 5 10 15 20 25 30 fcpu [mhz] i dd(run)hse [ma] 25c 85c 12 5 c figure 13. typ. i dd(run)hsi vs. v dd @f cpu = 16 mhz, periph = off figure 14. typ. i dd(wfi)hse vs. v dd @f cpu = 16 mhz, periph = on 0 1 2 3 4 2.5 3.5 4.5 5.5 6.5 vdd [v] idd(run)hsi [ma] 25c 85c 125c 0 1 2 3 4 5 6 2.5 3.5 4.5 5.5 6.5 vdd [v] idd(wfi)hse [ma] 25c 85c 125c figure 15. typ. i dd(wfi)hse vs. f cpu @v dd = 5.0 v, periph = on figure 16. typ. i dd(wfi)hsi vs. v dd @f cpu = 16 mhz, periph = off 0 1 2 3 4 5 6 0 5 10 15 20 25 30 fcpu [mhz] i dd(wfi)hse [ma] 25c 85c 12 5 c 0 0. 5 1 1. 5 2 2. 5 2. 5 3 3. 5 4 4. 5 5 5. 5 6 v dd [v] i dd(wfi)hsi [ma] 25c 85c 12 5 c
stm8af61xx, stm8af51xx electrical characteristics 67/100 11.3.2 external clock sources and timing characteristics hse user external clock subject to general operating conditions for v dd and t a . figure 17. hse external clock source hse crystal/ceramic resonator oscillator the hse clock can be supplied using a crystal/ce ramic resonator oscillator of up to 24 mhz. all the information given in this paragraph is based on characterization results with specified typical external components. in the application, the resonator and the load capacitors have to be placed as close as possible to the oscilla tor pins in order to minimize output distortion and start-up stabilizatio n time. refer to the crystal resona tor manufacturer for more details (frequency, package, accuracy...). table 24. hse user external clock characteristics symbol parameter conditions min typ max unit f hse_ext user external clock source frequency t a < 105 c 0 (1) 1. in case of css, the external clock must have a frequency above 500 khz. 24 mhz t a > 105 c 0 (1) 16 v hsedhl comparator hysteresis 0.1 x v dd v v hseh oscin input pin high level voltage 0.7 x v dd v dd v v hsel oscin input pin low level voltage v ss 0.3 x v dd i leak_hse oscin input leakage current v ss < v in < v dd -1 +1 a oscin f hse external clock stm8a source v hsel v hseh
electrical characteristics stm8af61xx, stm8af51xx 68/100 figure 18. hse oscillator circuit diagram hse oscillator critical g m formula r m : notional resistance (see crystal specification) l m : notional inductance (see crystal specification) c m : notional capacitance (s ee crystal specification) co: shunt capacitance (see crystal specification) c l1 = c l2 = c: grounded external capacitance g m >> g mcrit table 25. hse oscillator characteristics symbol parameter conditions min typ max unit r f feedback resistor 220 k ? c (1) recommended load capacitance (2) 20 pf i dd(hse) hse oscillator power consumption c = 20 pf 6 (startup) 2 (stabilized) ma c = 10 pf 6 (startup) 1.5 (stabilized) g m oscillator transconductance 5 ma/v t su(hse) (3) startup time v dd is stabilized 1ms 1. c is approximately equivalent to 2 x crystal cload. 2. the oscillator selection can be optimized in terms of supply current using a high qual ity resonator with small r m value. refer to crystal manufacturer for more details 3. t su(hse) is the start-up time measured from the moment it is enabled (by software) to a stabi lized 24 mhz oscillation is reached. this value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. oscout oscin f hse to core c l1 c l2 r f stm8a resonator consumption control g m r m c m l m c o resonator g mcrit 2 hse f () 2 r m 2co c + () 2 =
stm8af61xx, stm8af51xx electrical characteristics 69/100 11.3.3 internal clock sources and timing characteristics subject to general operating conditions for v dd and t a . high speed internal rc oscillator (hsi) figure 19. typical hsi frequency vs v dd @ four temperatures table 26. hsi oscillator characteristics symbol parameter conditions min typ max unit f hsi frequency 16 mhz acc hs hsi oscillator user trimming accuracy tr i m m e d b y t h e application for any v dd and t a conditions -1 (1) 1. tested in production 1 (1) % hsi oscillator accuracy (factory calibrated) v dd = 5.0 v, t a = 25c -1 (1) 1 (1) v dd = 5.0 v, 25 c t a 85 c 2 v dd = 5.0 v, 25 c t a 125 c -3 (1) 3 (1) v dd = 3.0 v v dd 5.5 v, -40 c t a 125 c -5 (1) 5 (1) t su(hsi) hsi oscillator wake-up time including calibration 2 (2) 2. guaranteed by design, not tested in production s -3% -2% -1% 0% 1% 2% 3% 2.5 3 3.5 4 4.5 5 5.5 6 v dd [v] hsi frequency variation [%] -40c 25c 85c 125c
electrical characteristics stm8af61xx, stm8af51xx 70/100 low speed internal rc oscillator (lsi) subject to general operating conditions for v dd and t a . figure 20. typical lsi frequency vs v dd @ room temperature table 27. lsi oscillator characteristics symbol parameter conditions min typ max unit f lsi frequency 112 128 144 khz t su(lsi) lsi oscillator wake-up time 7 (1) 1. data based on characterization results, not tested in production. s -3% -2% -1% 0% 1% 2% 3% 2.5 3 3.5 4 4.5 5 5.5 6 v dd [v] lsi frequency variation [%] 25c
stm8af61xx, stm8af51xx electrical characteristics 71/100 11.3.4 memory characteristics ram and hardware registers flash program memory/data eeprom memory general conditions: t a = -40 to 125 c. table 28. ram and hardware registers symbol parameter conditions min typ max unit v rm data retention mode (1) 1. minimum supply voltage without losing data stored in ram (in halt mode or under reset) or in hardware registers (only in halt mode). guaranteed by design, not tested in production. refer to table 18 on page 58 for the value of v it-max halt mode (or reset) 1.8 v table 29. flash program memory/data eeprom memory symbol parameter conditions min (1) 1. guaranteed by characterizati on, not tested in production. typ max unit v dd operating voltage (all modes, execution/write/erase) f cpu 24 mhz 3.0 5.5 v t prog standard programming time (including erase) for byte/word/block (1 byte/4 bytes/128 bytes) 66.6ms fast programming time for 1 block (128 bytes) 33.3ms t erase erase time for 1 block (128 bytes) 3 3.3 ms n rw program memory endurance erase/write cycles (2) 2. the physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation addresses a single byte. t a = 25 c 1 k cycles t a = 125 c 100 data memory endurance erase/write cycles (2) t a = 25 c 300 k t a = 125 c 100 k t a = 145 c 80 k t ret program memory after cycling t a = 25 c 40 years t a = 55 c 20 t a = 85 c 10 data memory retent ion after cycling at the endurance limits (t, n) full temperature range 1000 hours t reti intrinsic data retention t a = 25 c 40 years t a = 55 c 20 t a = 85 c 10
electrical characteristics stm8af61xx, stm8af51xx 72/100 11.3.5 i/o port pin characteristics general characteristics subject to general operating conditions for v dd and t a unless otherwise specified. all unused pins must be kept at a fixed voltage, us ing the output mode of the i/o for example or an external pull-up or pull-down resistor. table 30. i/o static characteristics symbol parameter conditions min typ max unit v il input low level voltage v dd = 5.0 v -0.3 v 0.3 x v dd v v ih input high level voltage 0.7 x v dd v dd + 0.3 v v v hys hysteresis (1) 0.1 x v dd mv v oh i = 3 ma standard i/0, v dd = 5 v v dd - 0.5 v v i = 1.5 ma standard i/0, v dd = 3 v v dd - 0.4 v v ol i = 8ma high sink and true open drain i/0, v dd = 5 v 0.5 i = 3 ma standard i/0, v dd = 5 v 0.6 i = 1.5 ma standard i/0, v dd = 3 v 0.4 r pu pull-up resistor v dd = 5 v, v in = v ss 35 50 65 k ? t r , t f rise and fall time (10% - 90%) fast i/os load = 50 pf 20 (2) ns standard and high sink i/os load = 50 pf 125 (2) ns i lkg input leakage current, analog and digital v ss v in v dd 1 (2) a i lkg ana analog input leakage current v ss v in v dd -40 c < t a < 125 c 250 (2) na i lkg(inj) leakage current in adjacent i/o (2) injection current 4 ma 1 (2) a 1. hysteresis voltage between schmitt trigger switching levels . based on characterization results, not tested in production. 2. data based on characterization results, not tested in production.
stm8af61xx, stm8af51xx electrical characteristics 73/100 figure 21. typical v il and v ih vs v dd @ four temperatures figure 22. typical pull-up resistance r pu vs v dd @ four temperatures figure 23. typical pull-up current i pu vs v dd @ four temperatures 0 1 2 3 4 5 6 2.5 3 3.5 4 4.5 5 5.5 6 v dd [v] v il / v ih [v] -40c 25c 85c 125c 30 35 40 45 50 55 60 2.53 3.544.55 5.56 v dd [v] pull-up resistance [k ohm ] -40c 25c 85c 125c 0 20 40 60 80 100 120 140 0123456 v dd [v] pull-up current [a] -40c 25c 85c 125c note: the pull-up is a pure resistor (slope goes through 0).
electrical characteristics stm8af61xx, stm8af51xx 74/100 typical output level curves figure 24 to figure 33 show typical output level curves measured with output on a single pin. figure 24. typ. v ol @ v dd = 3.3 v (standard ports) figure 25. typ. v ol @ v dd = 5.0 v (standard ports) 0 0.25 0.5 0.75 1 1.25 1.5 01234567 i ol [ma] v ol [v] -40c 25c 85c 125c 0 0.25 0.5 0.75 1 1.25 1.5 024681012 i ol [ma] v ol [v] -40c 25c 85c 125c figure 26. typ. v ol @ v dd = 3.3 v (true open drain ports) figure 27. typ. v ol @ v dd = 5.0 v (true open drain ports) 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 02468101214 i ol [ma] v ol [v] -40c 25c 85c 125c 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 0 5 10 15 20 25 i ol [ma] v ol [v] -40c 25c 85c 125c figure 28. typ. v ol @ v dd = 3.3 v (high sink ports) figure 29. typ. v ol @ v dd = 5.0 v (high sink ports) 0 0.25 0.5 0.75 1 1.25 1.5 02468101214 i ol [ma] v ol [v] -40c 25c 85c 125c 0 0.25 0.5 0.75 1 1.25 1.5 0 5 10 15 20 25 i ol [ma] v ol [v] -40c 25c 85c 125c
stm8af61xx, stm8af51xx electrical characteristics 75/100 figure 30. typ. v dd - v oh @ v dd = 3.3 v (standard ports) figure 31. typ. v dd - v oh @ v dd = 5.0 v (standard ports) 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 01234567 i oh [ma] v dd - v oh [v] -40c 25c 85c 125c 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 024681012 i oh [ma] v dd - v oh [v] -40c 25c 85c 125c figure 32. typ. v dd - v oh @ v dd = 3.3 v (high sink ports) figure 33. typ. v dd - v oh @ v dd = 5.0 v (high sink ports) 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 02468101214 i oh [ma] v dd - v oh [v] -40c 25c 85c 125c 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 0 5 10 15 20 25 i oh [ma] v dd - v oh [v] -40c 25c 85c 125c
electrical characteristics stm8af61xx, stm8af51xx 76/100 11.3.6 reset pin characteristics subject to general operating conditions for v dd and t a unless otherwise specified. figure 34. typical nrst v il and v ih vs v dd @ four temperatures table 31. nrst pin characteristics symbol parameter conditions min typ max unit v il(nrst) nrst input low level voltage (1) 1. data based on characterization results, not tested in production. v ss tbd (2) v v ih(nrst) nrst input high level voltage (1) tbd (2) v dd v ol(nrst) nrst output low level voltage (1) i ol =tbd (2) ma 2. tbd = to be determined. tbd (2) r pu(nrst) nrst pull-up resistor (3) 3. the r pu pull-up equivalent resistor is based on a resistive transistor 30 40 60 k ? v f(nrst) nrst input filtered pulse (4) 4. data guaranteed by design, not tested in production. tbd (2) ns v nf(nrst) nrst input not filtered pulse (4) tbd (2) s 0 1 2 3 4 5 6 2.5 3 3.5 4 4.5 5 5.5 6 v dd [v] v il / v ih [v] -40c 25c 85c 125c
stm8af61xx, stm8af51xx electrical characteristics 77/100 figure 35. typical nrst pull-up resistance r pu vs v dd @ four temperatures figure 36. typical nrst pull-up current i pu vs v dd @ four temperatures the reset network shown in figure 37 protects the device against parasitic resets. the user must ensure that the level on the nrst pin can go below the v il max. level specified in ta bl e 3 0 . otherwise the reset is not taken into account internally. figure 37. recommended reset pin protection 30 35 40 45 50 55 60 2.5 3 3.5 4 4.5 5 5.5 6 v dd [v] nrst pull-up resistance [k ohm ] -40c 25c 85c 125c 0 20 40 60 80 100 120 140 0123456 v dd [v] nrst pull-up current [a] -40c 25c 85c 125c 0.01? external reset circuit stm8a filter r pu v dd internal reset nrst
electrical characteristics stm8af61xx, stm8af51xx 78/100 11.3.7 tim 1, 2, 3, a nd 4 timer characteristics subject to general operating conditions for v dd , f master , and t a unless otherwise specified. table 32. tim 1, 2, 3 characteristics symbol parameter conditions min typ max unit t w(icap)in input capture pulse time (1) 1. not tested in production 2t master t res(tim) timer resolution time (1) 1t master f ext timer external clock frequency (1) 24 mhz res tim timer resolution (1) 16 bit t counter 16-bit counter clock period when internal clock is selected (1) 1t master t max_count maximum possible count (1) 65 536 t master
stm8af61xx, stm8af51xx electrical characteristics 79/100 11.3.8 spi serial peripheral interface unless otherwise specified, the parameters given in ta bl e 3 3 are derived from tests performed under ambient temperature, f master frequency and v dd supply voltage conditions. t master = 1/f master . refer to i/o port characteristics for more de tails on the input/output alternate function characteristics (nss , sck, mosi, miso). table 33. spi characteristics symbol parameter conditions min max unit f sck 1/t c(sck) spi clock frequency master mode 0 10 mhz slave mode 0 10 t r(sck) t f(sck) spi clock rise and fall time capacitive load: c = 30 pf 25 ns t su(nss) (1) nss setup time slave mode 4*t master t h(nss) (1) nss hold time slave mode 70 t w(sckh) (1) t w(sckl) (1) sck high and low time master mode, f master = 16 mhz, f sck = 8 mhz 110 140 t su(mi) (1) t su(si) (1) data input setup time master mode 5 slave mode 2 t h(mi) (1) t h(si) (1) data input hold time master mode, f master = 16 mhz, f sck = 8 mhz 7 slave mode, f master = 16 mhz, f sck = 8 mhz 3 t a(so) (1)(2) data output access time slave mode, f master = 16 mhz, f sck = 8 mhz 400 slave mode 4*t master t dis(so) (1)(3) data output disable time slave mode 25 t v(so) (1) data output valid time slave mode (after enable edge), f master = 16 mhz, f sck = 8 mhz 100 t v(mo) (1) data output valid time master mode (after enable edge), f master = 16 mhz, f sck = 8 mhz 3 t h(so) (1) data output hold time slave mode (after enable edge) 100 t h(mo) (1) master mode (after enable edge) 6 1. values based on design simulation and/or charac terization results, and not tested in production. 2. min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in hi-z.
electrical characteristics stm8af61xx, stm8af51xx 80/100 figure 38. spi timing diagram where slave mode and cpha = 0 figure 39. spi timing diagram where slave mode and cpha = 1 1. measurement points are at cmos levels: 0.3 v dd and 0.7 v dd . ai14134 sck input cpha= 0 mosi input miso out p ut cpha= 0 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in nss input t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) ai14135 sck input cpha=1 mosi input miso out p ut cpha=1 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) nss input
stm8af61xx, stm8af51xx electrical characteristics 81/100 figure 40. spi timing diagram - master mode 1. measurement points are at cmos levels: 0.3 v dd and 0.7 v dd . ai14136 sck input cpha= 0 mosi outut miso inp ut cpha= 0 ms bin m sb out bi t6 in lsb out lsb in cpol=0 cpol=1 b i t1 out nss input t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t h(mi) high sck input cpha=1 cpha=1 cpol=0 cpol=1 t su(mi) t v(mo) t h(mo)
electrical characteristics stm8af61xx, stm8af51xx 82/100 11.3.9 i 2 c interface characteristics table 34. i 2 c characteristics symbol parameter standard mode i 2 c fast mode i 2 c (1) 1. f master , must be at least 8 mhz to achieve max fast i 2 c speed (400 khz) unit min (2) 2. data based on standard i 2 c protocol requirement, not tested in production max (2) min (2) max (2) t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0 (3) 3. the maximum hold time of the start condition has only to be met if the interface does not stretch the low time 0 (4) 4. the device must internally provide a hold time of at least 300 ns for th e sda signal in order to bridge the undefined region of the falling edge of scl 900 (3) t r(sda) t r(scl) sda and scl rise time (v dd 3 ... 5.5 v) 1000 300 t f(sda) t f(scl) sda and scl fall time (v dd 3 ... 5.5 v) 300 300 t h(sta) start condition hold time 4.0 0.6 s t su(sta) repeated start condition setup time 4.7 0.6 t su(sto) stop condition setup time 4.0 0.6 s t w(sto:sta) stop to start condition time (bus free) 4.7 1.3 s c b capacitive load for each bus line 400 400 pf
stm8af61xx, stm8af51xx electrical characteristics 83/100 11.3.10 10-bit adc characteristics subject to general operating conditions for v dda , f master , and t a unless otherwise specified. table 35. adc characteristics symbol parameter conditions min typ max unit f adc adc clock frequency 2 mhz v dda analog supply 3 5.5 v v ref+ positive reference voltage 2.75 v dda v v ref- negative reference voltage v ssa 0.5 v v ain conversion voltage range (1) 1. during the sample time the input capacitance c ain (3 pf max) can be char ged/discharged by the external source. the internal resistance of the analog source must allow the capacitance to reach its final voltage level within t s. after the end of the sample time t s , changes of the analog input voltage have no effect on the conversion result. values for the sample clock t s depend on programming. v ssa v dda v devices with external v ref+ / v ref- pins v ref- v ref+ v c adc internal sample and hold capacitor 3pf t s (1) sampling time (3 x 1/f adc ) f adc = 2 mhz 1.5 s t stab wake-up time from standby 7 s t conv total conversion time including sampling time (14 x 1/f adc ) f adc = 2 mhz 7 s
electrical characteristics stm8af61xx, stm8af51xx 84/100 figure 41. adc accura cy characteristics 1. example of an actual transfer curve 2. the ideal transfer curve 3. end point correlation line e t = total unadjusted error: maximum deviation betw een the actual and the ideal transfer curves. e o = offset error: deviation between the fi rst actual transition and the first ideal one. e g = gain error: deviation between the last ideal transition and the last actual one. e d = differential linearity error: maximum dev iation between actual steps and the ideal one. e l = integral linearity error: maximum deviation between any actual transition an d the end point correlation line. table 36. adc accuracy with r ain < 10 k ? r ain , v dda = 3.3 v symbol parameter conditions typ max unit |e t | total unadjusted error (1) f adc = 2 mhz 1.5 tbd (1) 1. tbd = to be determined lsb |e o | offset error (1) 1.1 tbd (1) |e g | gain error (1) -0.2/0.6 tbd (1) |e d | differential linearity error (1) 0.9 tbd (1) |e l | integral linearity error (1) 1 tbd (1) table 37. adc accuracy with r ain < 10 k ? , v dda = 5 v symbol parameter conditions typ max unit |e t | total unadjusted error (1) 1. adc accuracy vs. injection current: any positive or negat ive injection current within the limits specified for i inj(pin) and i inj(pin) in section 11.3.5 does not affect the adc accuracy. f adc = 2 mhz 1.4 3 lsb |e o | offset error (1) 0.8 2 |e g | gain error (1) 0.1 1 |e d | differential linearity error (1) 0.9 2 |e l | integral linearity error (1) 0.7 2 e o e g 1lsb ideal 1lsb ideal v dda v ssa ? 1024 ---------------------------------------- - = 1023 1022 1021 5 4 3 2 1 0 7 6 1234567 1021102210231024 (1) (2) e t e d e l (3) v dda v ssa
stm8af61xx, stm8af51xx electrical characteristics 85/100 figure 42. typical application with adc 11.3.11 emc characteristics susceptibility tests ar e performed on a sample basis du ring product ch aracterization. functional ems (electromagnetic susceptibility) while executing a simple application (toggling 2 leds through i/o ports), the product is stressed by two electromagnetic events unt il a failure occurs (indicated by the leds). esd : electrostatic discharge (positive and negati ve) is applied on all pins of the device until a functional disturbance occurs. this test conforms with the iec 1000-4-2 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a function al disturbance occurs. this test conforms with the iec 1000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in the table below based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are per formed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the us er applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations the software flowchart must include the management of runaway conditions such as: corrupted program counter unexpected reset critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be recovered by applying a low state on the nr st pin or the oscilla tor pins for 1 second. to complete these trials, esd stress can be app lied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). ainx stm8a v dd i l ?1? v t 0.6v v t 0.6v c adc v ain r ain 10-bit a/d conversion c ain
electrical characteristics stm8af61xx, stm8af51xx 86/100 electromagnetic interference (emi) emission tests conform to the sae j 1752/3 stan dard for test software , board layout and pin loading. absolute maximum ratings (electrical sensitivity) based on two different tests (esd and lu) using specific measurement methods, the product is stressed to determine its performance in terms of electrical sensitivity. for more details, refer to the ap plication note an1181. electrostatic discharge (esd) electrostatic discharges (3 positive then 3 n egative pulses separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). this test conforms to the jesd22-a114a/a115a standard. for more details, refer to the application note an1181. table 38. ems data symbol parameter conditions level/class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, t a = 25 c, f master = 16 mhz (hsi clock), conforms to iec 1000-4-2 3b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, t a = 25 c, f master = 16 mhz (hsi clock), conforms to iec 1000-4-4 4a table 39. emi data symbol parameter conditions unit general conditions monitored frequency band max f cpu (1) 8 mhz 16 mhz 24 mhz s emi peak level v dd = 5 v, t a = 25 c, lqfp80 package conforming to sae j 1752/3 0.1 mhz to 30 mhz 15 17 22 dbv 30 mhz to 130 mhz 18 22 16 130 mhz to 1 ghz -1 3 5 sae emi level 2 2.5 2.5 - 1. data based on characterization results, not tested in production.
stm8af61xx, stm8af51xx electrical characteristics 87/100 static latch-up two complementary static tests are required on 10 parts to assess the latch-up performance. a supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable i/o pin) are performed on each sample. this test conforms to the eia/jesd 78 ic la tch-up standard. for more details, refer to the application note an1181. table 40. esd absolute maximum ratings symbol ratings conditions class maximum value (1) 1. data based on characterization results, not tested in production unit v esd(hbm) electrostatic discharge voltage (human body model) t a = 25c, conforming to jesd22-a114 3a 4000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a = 25c, conforming to jesd22-c101 3 500 v esd(mm) electrostatic discharge voltage (machine model) t a = 25c, conforming to jesd22-a115 b 200 table 41. electrical sensitivities symbol parameter conditions class (1) 1. class description: a class is an stmi croelectronics internal specification. all its limits are higher than the jedec specifications, that means when a device belongs to class a it exceeds the jedec standard. b class strictly covers all the jedec criteria (international standard). lu static latch-up class t a = 25 c a t a = 85 c a t a = 125 c a t a = 145 c a
electrical characteristics stm8af61xx, stm8af51xx 88/100 11.4 thermal characteristics the maximum chip junction temperature (t jmax ) must never exceed the values given in table 17: general operating conditions on page 57 . the maximum chip-junction temperature, t jmax , in degrees celsius, may be calculated using the following equation: t jmax = t amax + (p dmax x ja ) where: ?t amax is the maximum ambient temperature in c ? ja is the package junction-to-ambient thermal resistance in c/w ?p dmax is the sum of p intmax and p i/omax (p dmax = p intmax + p i/omax ) ?p intmax is the product of i dd and v dd , expressed in watts. this is the maximum chip internal power. ?p i/omax represents the maximum power dissipation on output pins where: p i/omax = (v ol *i ol ) + ((v dd -v oh )*i oh ), taking into account the actual v ol /i ol and v oh /i oh of the i/os at low and high level in the application. 11.4.1 reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). available from www.jedec.org. table 42. thermal characteristics (1) 1. thermal resistances are based on jedec jesd51- 2 with 4-layer pcb in a natural convection environment. symbol parameter value unit ja thermal resistance junction-ambient lqfp 80 - 14 x 14 mm 38 c/w ja thermal resistance junction-ambient lqfp 64 - 10 x 10 mm 46 c/w ja thermal resistance junction-ambient lqfp 48 - 7 x 7 mm 57 c/w ja thermal resistance junction-ambient lqfp 32 - 7 x 7 mm 59 c/w
stm8af61xx, stm8af51xx electrical characteristics 89/100 11.4.2 selecting the pro duct temperature range when ordering the microcontroller, the temper ature range is specified in the order code (see figure 47: stm8a order codes on page 95 ). the following example shows how to calculate the temperature range needed for a given application. assuming the following application conditions: maximum ambient temperature t amax = 82 c (measured according to jesd51-2), i ddmax = 8 ma, v dd = 5 v, maximum 20 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v p intmax = 8 ma x 5 v= 400 mw p iomax = 20 x 8 ma x 0.4 v = 64 mw this gives: p intmax = 400 mw and p iomax 64 mw: p dmax = 400 mw + 64 mw thus: p dmax = 464 mw using the values obtained in table 42: thermal characteristics on page 88 t jmax is calculated as follows: ? for lqfp64 46c/w t jmax = 82 c + (46 c/w x 464 mw) = 82c + 21c = 103 c this is within the range of the suffix b version parts (-40 < t j < 105 c). parts must be ordered at least with the temperature range suffix b.
package characteristics stm8af61xx, stm8af51xx 90/100 12 package characteristics to meet environmental requirements, st offers these devices in ecopack ? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack ? specifications are available at www.st.com .
stm8af61xx, stm8af51xx package characteristics 91/100 12.1 package mechanical data figure 43. 80-pin low profile quad flat package (14 x 14) table 43. 80-pin low profile quad flat package mechanical data dim. mm inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits min typ max min typ max a - - 1.60 - - 0.0630 a1 0.05 - 0.15 0.0020 - 0.0060 a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.22 0.32 0.38 0.0087 0.0126 0.0150 c 0.09 - 0.20 0.0035 - 0.0079 d 15.80 16.00 16.20 0.6220 0.6299 0.6378 d1 13.80 14.00 14.20 0.5433 0.5512 0.5591 d3 - 12.35 - - 0.4862 - e 15.80 16.00 16.20 0.6220 0.6299 0.6378 e1 13.80 14.00 14.20 0.5433 0.5512 0.5591 e3 - 12.35 - - 0.4862 - e - 0.65 - - 0.0256 - l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 - 1.00 - - 0.0394 - ccc - - 0.10 - - 0.0039 k03.5703.57 1s_me l a1 k l1 c a a2 ccc c d d1 d3 e3 e1 e 40 41 60 61 b 80 1 pin 1 identification
package characteristics stm8af61xx, stm8af51xx 92/100 figure 44. 64-pin low profile quad flat package (10 x 10) 1. available only for stm8a products with up to 64 kbytes flash table 44. 64-pin low profile quad flat package mechanical data dim. mm inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits min typ max min typ max a 1.60 0.0630 a1 0.05 0.15 0.0020 0.0059 a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 0.20 0.0035 0.0079 d 12.00 0.4724 d1 10.00 0.3937 e 12.00 0.4724 e1 10.00 0.3937 e 0.50 0.0197 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0394 l1 l a a2 a1 b e c d d1 e e1 pin 1 identification m x 45 seating plane (0.1 x 0.004 mm)
stm8af61xx, stm8af51xx package characteristics 93/100 figure 45. 48-pin low profile quad flat package (7 x 7) table 45. 48-pin low profile quad flat package mechanical data dim. mm inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits min typ max min typ max a 1.60 0.0630 a1 0.05 0.15 0.0020 0.0059 a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 0.20 0.0035 0.0079 d 9.00 0.3543 d1 7.00 0.2756 e 9.00 0.3543 e1 7.00 0.2756 e 0.50 0.0197 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0394 e e1 d d1 l1 l c e b a1 a2 a
package characteristics stm8af61xx, stm8af51xx 94/100 figure 46. 32-pin low profile quad flat package (7 x 7) table 46. 32-pin low profile quad flat package mechanical data dim. mm inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits min typ max min typ max a 1.60 0.0630 a1 0.05 0.15 0.0020 0.0059 a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.30 0.37 0.45 0.0118 0.0146 0.0177 c 0.09 0.20 0.0035 0.0079 d 9.00 0.3543 d1 7.00 0.2756 e 9.00 0.3543 e1 7.00 0.2756 e 0.80 0.0315 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0394 c l l1 b e a1 a2 a e e1 d d1
stm8af61xx, stm8af51xx ordering information 95/100 13 ordering information figure 47. stm8a order codes 1. customer specific fastrom code product family stm8a....8-bit microcontroller program memory type f....flash + eeprom p....fastrom no eeprom h....flash no eeprom q....fastrom + eeprom device family 5x - can/lin 6x - lin only memory size 2....8 kbyte 4....16 kbyte 6....32 kbyte 7....48 kbyte 8....64 kbyte 9....96 kbyte a....128 kbyte b....256 kbyte pin count 3....20 pins 6....32 pins 7....44 pins 8....48 pins 9....64 pins a....80 pins b....100 pins c....128 pins package type t.....lqfp u....qfn packaging y.... tray u.... tube r.... tape and reel x.... tape and reel x90 temperature range a....-40 c to +85 c b....-40 c to +105 c c....-40 c to +125 c d....-40 c to +145 c stm8a f 61 a a t d xxx (1) y
stm8 development tools stm8af61xx, stm8af51xx 96/100 14 stm8 development tools development tools for the stm8a microcontrollers include the stice emulation system offeri ng tracing and code profiling stvd high-level language debugger including assembler and visual development environment - seamless integration of third party c compilers stvp flash programming software in addition, the stm8a comes with starter ki ts, evaluation boards and low-cost in-circuit debugging/programming tools. 14.1 emulation and in-circuit debugging tools the stm8 tool line includes the stice emulation system offering a complete range of emulation and in-circuit debugging features on a platform that is designed for versatility and cost-effectiveness. in addition, stm8a applicat ion development is supported by a low-cost in-circuit debugger/programmer. the stice is the fourth generation of full-featured emulators from stmicroelectronics. it offers new advanced debuggin g capabilities including tracing, profiling and code coverage analysis to help detect execution bottlenecks and dead code. in addition, stice offers in-circuit debugging and programming of stm8a microcontrollers via the stm8 single wire interface module (swim), which allows non-intrusive debugging of an application while it runs on the target microcontroller. for improved cost effectiveness, stice is based on a modular design that allows you to order exactly what you need to meet your development requirements and to adapt your emulation system to support existing and future st microcontrollers. stice key features program and data trace recording up to 128 k records advanced breakpoints with up to 4 levels of conditions data breakpoints real-time read/write of all device ressources during emulation occurrence and time profiling and code coverage analysis (new features) in-circuit debugging/programming via swim protocol 8-bit probe analyzer 1 input and 2 output triggers usb 2.0 high speed interface to host pc power supply follower managing application voltages between 1.62 to 5.5 v modularity that allows you to specify the components you need to meet your development requirements and adapt to future requirements supported by free software tools that include integrated development environment (ide), programming software interface and assembler for stm8
stm8af61xx, stm8af51xx stm8 development tools 97/100 14.2 software tools stm8 development tools are supported by a complete, free software package from stmicroelectronics that includes st visual develop (stvd) ide and the st visual program- mer (stvp) software interface. stvd provides seamless integration of the cosmic c com- piler for stm8, which is available in a free version that outputs up to 16 kbytes of code. 14.2.1 stm8 toolset stm8 toolset with stvd integrated development environment and stvp programming software is available for free download at www.st.com/mcu. this package includes: st visual develop ? full-featured integrated development environment from stmicroelectronics, featuring seamless integration of c and asm toolsets full-featured debugger project management syntax highlighting editor integrated programming interface support of advanced emulati on features for stice such as code profiling and coverage st visual programmer (stvp) ? easy-to-use, unlimited graphic al interface allowing read, write and verify of your stm8a microcontroller?s flash memory. stvp also offers project mode for saving programming configurations and automating programming sequences. 14.2.2 c and assembly toolchains control of c and assembly toolchains is seam lessly integrated into the stvd integrated development environment, making it possible to configure and control the building of your application directly from an easy-to-use graphical interface. available toolchains include: c compiler for stm8 ? available in a free version that outputs up to 16 kbytes of code. for more information, see www.cosmic-software.com, www.raisonance.com stm8 assembler linker ? free assembly toolchain included in the stm8 toolset, which allows you to assemble and link your application source code. 14.3 programming tools during the development cycle, stice provides in-circuit programming of the stm8a flash microcontroller on your application board via the swim protocol. additional tools are to include a low-cost in-circuit programmer as well as st socket boards, which provide dedicated programming platforms with sockets for programming your stm8a. for production environments, programmers w ill include a complete range of gang and automated programming solutions from third-party tool developers already supplying programmers for the stm8 family.
revision history stm8af61xx, stm8af51xx 98/100 15 revision history table 47. document revision history date revision changes 31-jan-2008 rev 1 initial release 22-aug-2008 rev 2 added ?h? products to the datasheet (flash no eeprom). features on page 1 : updated memories , reset and supply management , communication interfaces and i/os ; reduced wakeup pins by 1. ta bl e 1 : removed stm8af6168, stm8af6148, stm8af6166, stm8af6146, stm8af5168, st m8af5186, stm8af5176, and stm8af5166. section 1 , section 5 , section 6.2.1 , ta bl e 1 3 , and section 10 : updated reference documentation: rm0009, pm0047, and um0470. section 2 : added information about peak performance. section 3 : removed stm8a common features table. ta bl e 2 : removed stm8af5186t, stm8af5176t, stm8af5168t, and stm8af5166t. ta bl e 3 : removed stm8af6168t, stm8af6166t, stm8af6148t, and stm8af6146t. section 5 : made minor content changes and improved readability and layout. section 5.4.3 : major modification, tmu included. section 5.6.2 : user triming updated. section 5.6.3 : lsi as cpu clock added. section 5.6.4 , section 5.6.5 : maximum frequency conditional 32 kbyte/128 kbyte. section 5.8 : scan for 128 kbyte removed. section 5.9 , section 5.9.3 : spi 10 mb/s. figure 3 , figure 4 , and figure 5 : amended footnote 1. ta bl e 5 : hs output changed from 20 ma to 8 ma. section 7 : corrected figure 7: register and memory map ; removed address list; added ta bl e 7 . section 11.3.1 note on typical/wc values added. ta bl e 1 0 : replaced the source blocks ?simple usart?, ?very low-end timer (timer 4)?, and ?eeprom? with ?linuart?, ?timer4? and ?reserved? respectively, added tmu registers. ta bl e 1 2 : updated opt6 and nopt6, added opt7 to 17 (tmu, bl) ta bl e 1 3 : updated opt1 ubc[7:0], opt4 ckawusel, opt4 prsc [1:0], and opt6, added opt7 to 16 (tmu). ta bl e 1 5 : amended footnotes. ta bl e 1 7 : added parameter ?voltage and current operating conditions?. ta bl e 1 8 : amended footnotes. ta bl e 1 9 : replaced. ta bl e 2 0 : amended maximum data and footnotes. ta bl e 2 1 : replaced. ta bl e 2 2 : added and amended i dd(run) data; amended i dd(wfi) data; amended footnotes. ta bl e 2 3 : filled in, amended maximum data and footnotes. figure 11 to figure 16 : info on peripheral activity added. ta bl e 2 4 : modified f hse_ext data and added v hsedhl data.
stm8af61xx, stm8af51xx revision history 99/100 22-aug-2008 rev 2 cont?d ta bl e 2 6 : removed acc hsi parameters and replaced with acc hs parameters; amended data and footnotes. ta bl e 2 8 : amended data. ta bl e 2 9 : updated names and data of n rw and t ret parameters. ta bl e 3 0 : added v oh and v ol parameters; updated i lkg ana parameter. removed: output driving current (standard ports) , output driving current (true open drain ports) , and output driving current (high sink ports) . ta bl e 3 5 : updated f adc , t s , and t conv data. ta bl e 3 6 : removed the 4-mhz condition from all parameters. ta bl e 3 7 : removed the 4-mhz condition from all parameters; updated footnote 1 and removed footnote 2. ta bl e 4 1 : added data for t a = 145 c. figure 47 : updated memory size, pin count and package type information. 16-sep-2008 rev 3 replaced the salestype ?stm8h61 xx? with ?stm8ah61xx on the first page. added ?part numbers? to heading rows of table 1: device summary . updated the 80-pin package silhouette on page 1 in line with poa 0062342-revd. ta bl e 1 0 : renamed ?tmu key registers 0-7 [7:0]? as ?tmu key registers 1-8 [7:0]? section 10 : updated introductory text concerning option bytes which do not need to be saved in a complementary form. ta bl e 1 2 : renamed the option bits ?t mu[0:3]?, ?ntmu[0:3]?, and ?tmu_key 0-7 [7:0]? as ?tmu[3:0]?, ?ntmu[3:0] ?, and ?tmu_key 1-8 [7:0]? respectively. ta bl e 1 3 : updated values of option byte 5 (hsecnt[7:0]); inversed the description of option byte 6 (tmu[3:0]); renamed option bytes 8 to 15 ?tmu_key 0-7 [7:0]?, as ?tmu_key 1-8 [7:0]?. updated 80-pin package information in line with poa 0062342-revd in figure 43 and ta bl e 4 3 . table 47. document revision history (continued) date revision changes
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